315 lines
7.5 KiB
C
315 lines
7.5 KiB
C
/*
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* Copyright (c) 2014-2015 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "hns_dsaf_misc.h"
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#include "hns_dsaf_mac.h"
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#include "hns_dsaf_reg.h"
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#include "hns_dsaf_ppe.h"
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void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
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u16 speed, int data)
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{
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int speed_reg = 0;
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u8 value;
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if (!mac_cb) {
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pr_err("sfp_led_opt mac_dev is null!\n");
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return;
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}
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if (!mac_cb->cpld_vaddr) {
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dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
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mac_cb->mac_id);
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return;
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}
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if (speed == MAC_SPEED_10000)
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speed_reg = 1;
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value = mac_cb->cpld_led_value;
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if (link_status) {
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dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
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dsaf_set_field(value, DSAF_LED_SPEED_M,
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DSAF_LED_SPEED_S, speed_reg);
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dsaf_set_bit(value, DSAF_LED_DATA_B, data);
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if (value != mac_cb->cpld_led_value) {
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dsaf_write_b(mac_cb->cpld_vaddr, value);
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mac_cb->cpld_led_value = value;
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}
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} else {
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dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
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mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
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}
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}
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void cpld_led_reset(struct hns_mac_cb *mac_cb)
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{
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if (!mac_cb || !mac_cb->cpld_vaddr)
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return;
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dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
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mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
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}
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int cpld_set_led_id(struct hns_mac_cb *mac_cb,
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enum hnae_led_state status)
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{
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switch (status) {
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case HNAE_LED_ACTIVE:
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mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
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dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
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CPLD_LED_ON_VALUE);
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dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
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return 2;
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case HNAE_LED_INACTIVE:
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dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
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CPLD_LED_DEFAULT_VALUE);
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dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
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break;
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default:
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break;
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}
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return 0;
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}
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#define RESET_REQ_OR_DREQ 1
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void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
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{
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u32 xbar_reg_addr;
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u32 nt_reg_addr;
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if (!val) {
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xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
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nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
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} else {
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xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
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nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
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}
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dsaf_write_reg(dsaf_dev->sc_base, xbar_reg_addr,
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RESET_REQ_OR_DREQ);
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dsaf_write_reg(dsaf_dev->sc_base, nt_reg_addr,
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RESET_REQ_OR_DREQ);
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}
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void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
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{
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u32 reg_val = 0;
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u32 reg_addr;
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if (port >= DSAF_XGE_NUM)
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return;
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reg_val |= RESET_REQ_OR_DREQ;
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reg_val |= 0x2082082 << port;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
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dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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}
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void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
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u32 port, u32 val)
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{
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u32 reg_val = 0;
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u32 reg_addr;
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if (port >= DSAF_XGE_NUM)
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return;
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reg_val |= XGMAC_TRX_CORE_SRST_M << port;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
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dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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}
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void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
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{
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u32 reg_val_1;
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u32 reg_val_2;
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if (port >= DSAF_GE_NUM)
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return;
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if (port < DSAF_SERVICE_NW_NUM) {
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reg_val_1 = 0x1 << port;
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/* there is difference between V1 and V2 in register.*/
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if (AE_IS_VER1(dsaf_dev->dsaf_ver))
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reg_val_2 = 0x1041041 << port;
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else
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reg_val_2 = 0x2082082 << port;
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if (val == 0) {
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_GE_RESET_REQ1_REG,
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reg_val_1);
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_GE_RESET_REQ0_REG,
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reg_val_2);
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} else {
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_GE_RESET_DREQ0_REG,
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reg_val_2);
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_GE_RESET_DREQ1_REG,
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reg_val_1);
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}
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} else {
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reg_val_1 = 0x15540 << (port - 6);
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reg_val_2 = 0x100 << (port - 6);
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if (val == 0) {
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_GE_RESET_REQ1_REG,
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reg_val_1);
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_PPE_RESET_REQ_REG,
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reg_val_2);
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} else {
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_GE_RESET_DREQ1_REG,
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reg_val_1);
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dsaf_write_reg(dsaf_dev->sc_base,
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DSAF_SUB_SC_PPE_RESET_DREQ_REG,
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reg_val_2);
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}
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}
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}
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void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
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{
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u32 reg_val = 0;
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u32 reg_addr;
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reg_val |= RESET_REQ_OR_DREQ << port;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
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dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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}
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void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
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{
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int comm_index = ppe_common->comm_index;
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struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
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u32 reg_val;
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u32 reg_addr;
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if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
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reg_val = RESET_REQ_OR_DREQ;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
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} else {
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reg_val = 0x100 << (comm_index - 1);
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if (val == 0)
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reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
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}
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dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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}
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/**
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* hns_mac_get_sds_mode - get phy ifterface form serdes mode
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* @mac_cb: mac control block
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* retuen phy interface
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*/
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phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
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{
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u32 hilink3_mode;
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u32 hilink4_mode;
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void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;
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int dev_id = mac_cb->mac_id;
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phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
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hilink3_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK3_REG);
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hilink4_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK4_REG);
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if (dev_id >= 0 && dev_id <= 3) {
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if (hilink4_mode == 0)
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phy_if = PHY_INTERFACE_MODE_SGMII;
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else
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phy_if = PHY_INTERFACE_MODE_XGMII;
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} else if (dev_id >= 4 && dev_id <= 5) {
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if (hilink3_mode == 0)
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phy_if = PHY_INTERFACE_MODE_SGMII;
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else
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phy_if = PHY_INTERFACE_MODE_XGMII;
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} else {
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phy_if = PHY_INTERFACE_MODE_SGMII;
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}
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dev_dbg(mac_cb->dev,
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"hilink3_mode=%d, hilink4_mode=%d dev_id=%d, phy_if=%d\n",
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hilink3_mode, hilink4_mode, dev_id, phy_if);
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return phy_if;
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}
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/**
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* hns_mac_config_sds_loopback - set loop back for serdes
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* @mac_cb: mac control block
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* retuen 0 == success
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*/
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int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
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{
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/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
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* port 4-7 hilink3 base is serdes_vaddr + 0x00200000
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*/
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u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
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(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
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const u8 lane_id[] = {
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0, /* mac 0 -> lane 0 */
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1, /* mac 1 -> lane 1 */
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2, /* mac 2 -> lane 2 */
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3, /* mac 3 -> lane 3 */
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2, /* mac 4 -> lane 2 */
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3, /* mac 5 -> lane 3 */
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0, /* mac 6 -> lane 0 */
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1 /* mac 7 -> lane 1 */
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};
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#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
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u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
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int sfp_prsnt;
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int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
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if (!mac_cb->phy_node) {
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if (ret)
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pr_info("please confirm sfp is present or not\n");
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else
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if (!sfp_prsnt)
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pr_info("no sfp in this eth\n");
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}
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dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
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return 0;
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}
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