1313 lines
30 KiB
C
1313 lines
30 KiB
C
/*
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Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
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Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
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Copyright (C) 2009 TurboSight.com
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/firmware.h>
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#include "dvb_frontend.h"
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#include "ds3000.h"
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) \
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printk(args); \
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} while (0)
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/* as of March 2009 current DS3000 firmware version is 1.78 */
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/* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
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#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
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#define DS3000_SAMPLE_RATE 96000 /* in kHz */
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#define DS3000_XTAL_FREQ 27000 /* in kHz */
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/* Register values to initialise the demod in DVB-S mode */
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static u8 ds3000_dvbs_init_tab[] = {
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0x23, 0x05,
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0x08, 0x03,
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0x0c, 0x00,
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0x21, 0x54,
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0x25, 0x82,
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0x27, 0x31,
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0x30, 0x08,
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0x31, 0x40,
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0x32, 0x32,
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0x33, 0x35,
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0x35, 0xff,
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0x3a, 0x00,
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0x37, 0x10,
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0x38, 0x10,
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0x39, 0x02,
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0x42, 0x60,
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0x4a, 0x40,
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0x4b, 0x04,
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0x4d, 0x91,
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0x5d, 0xc8,
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0x50, 0x77,
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0x51, 0x77,
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0x52, 0x36,
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0x53, 0x36,
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0x56, 0x01,
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0x63, 0x43,
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0x64, 0x30,
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0x65, 0x40,
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0x68, 0x26,
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0x69, 0x4c,
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0x70, 0x20,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x40,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x60,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x80,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0xa0,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x1f,
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0x76, 0x00,
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0x77, 0xd1,
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0x78, 0x0c,
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0x79, 0x80,
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0x7f, 0x04,
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0x7c, 0x00,
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0x80, 0x86,
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0x81, 0xa6,
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0x85, 0x04,
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0xcd, 0xf4,
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0x90, 0x33,
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0xa0, 0x44,
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0xc0, 0x18,
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0xc3, 0x10,
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0xc4, 0x08,
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0xc5, 0x80,
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0xc6, 0x80,
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0xc7, 0x0a,
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0xc8, 0x1a,
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0xc9, 0x80,
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0xfe, 0x92,
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0xe0, 0xf8,
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0xe6, 0x8b,
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0xd0, 0x40,
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0xf8, 0x20,
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0xfa, 0x0f,
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0xfd, 0x20,
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0xad, 0x20,
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0xae, 0x07,
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0xb8, 0x00,
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};
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/* Register values to initialise the demod in DVB-S2 mode */
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static u8 ds3000_dvbs2_init_tab[] = {
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0x23, 0x0f,
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0x08, 0x07,
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0x0c, 0x00,
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0x21, 0x54,
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0x25, 0x82,
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0x27, 0x31,
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0x30, 0x08,
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0x31, 0x32,
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0x32, 0x32,
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0x33, 0x35,
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0x35, 0xff,
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0x3a, 0x00,
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0x37, 0x10,
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0x38, 0x10,
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0x39, 0x02,
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0x42, 0x60,
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0x4a, 0x80,
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0x4b, 0x04,
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0x4d, 0x81,
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0x5d, 0x88,
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0x50, 0x36,
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0x51, 0x36,
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0x52, 0x36,
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0x53, 0x36,
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0x63, 0x60,
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0x64, 0x10,
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0x65, 0x10,
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0x68, 0x04,
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0x69, 0x29,
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0x70, 0x20,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x40,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x60,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x80,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0xa0,
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0x71, 0x70,
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0x72, 0x04,
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0x73, 0x00,
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0x70, 0x1f,
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0xa0, 0x44,
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0xc0, 0x08,
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0xc1, 0x10,
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0xc2, 0x08,
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0xc3, 0x10,
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0xc4, 0x08,
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0xc5, 0xf0,
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0xc6, 0xf0,
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0xc7, 0x0a,
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0xc8, 0x1a,
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0xc9, 0x80,
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0xca, 0x23,
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0xcb, 0x24,
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0xce, 0x74,
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0x90, 0x03,
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0x76, 0x80,
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0x77, 0x42,
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0x78, 0x0a,
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0x79, 0x80,
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0xad, 0x40,
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0xae, 0x07,
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0x7f, 0xd4,
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0x7c, 0x00,
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0x80, 0xa8,
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0x81, 0xda,
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0x7c, 0x01,
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0x80, 0xda,
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0x81, 0xec,
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0x7c, 0x02,
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0x80, 0xca,
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0x81, 0xeb,
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0x7c, 0x03,
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0x80, 0xba,
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0x81, 0xdb,
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0x85, 0x08,
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0x86, 0x00,
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0x87, 0x02,
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0x89, 0x80,
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0x8b, 0x44,
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0x8c, 0xaa,
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0x8a, 0x10,
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0xba, 0x00,
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0xf5, 0x04,
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0xfe, 0x44,
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0xd2, 0x32,
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0xb8, 0x00,
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};
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struct ds3000_state {
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struct i2c_adapter *i2c;
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const struct ds3000_config *config;
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struct dvb_frontend frontend;
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u8 skip_fw_load;
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/* previous uncorrected block counter for DVB-S2 */
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u16 prevUCBS2;
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};
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static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
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{
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u8 buf[] = { reg, data };
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struct i2c_msg msg = { .addr = state->config->demod_address,
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.flags = 0, .buf = buf, .len = 2 };
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int err;
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dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
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err = i2c_transfer(state->i2c, &msg, 1);
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if (err != 1) {
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printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
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" value == 0x%02x)\n", __func__, err, reg, data);
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return -EREMOTEIO;
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}
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return 0;
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}
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static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
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{
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u8 buf[] = { reg, data };
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struct i2c_msg msg = { .addr = 0x60,
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.flags = 0, .buf = buf, .len = 2 };
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int err;
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dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
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ds3000_writereg(state, 0x03, 0x11);
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err = i2c_transfer(state->i2c, &msg, 1);
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if (err != 1) {
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printk("%s: writereg error(err == %i, reg == 0x%02x,"
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" value == 0x%02x)\n", __func__, err, reg, data);
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return -EREMOTEIO;
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}
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return 0;
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}
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/* I2C write for 8k firmware load */
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static int ds3000_writeFW(struct ds3000_state *state, int reg,
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const u8 *data, u16 len)
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{
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int i, ret = -EREMOTEIO;
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struct i2c_msg msg;
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u8 *buf;
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buf = kmalloc(33, GFP_KERNEL);
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if (buf == NULL) {
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printk(KERN_ERR "Unable to kmalloc\n");
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ret = -ENOMEM;
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goto error;
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}
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*(buf) = reg;
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msg.addr = state->config->demod_address;
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msg.flags = 0;
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msg.buf = buf;
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msg.len = 33;
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for (i = 0; i < len; i += 32) {
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memcpy(buf + 1, data + i, 32);
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dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1) {
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printk(KERN_ERR "%s: write error(err == %i, "
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"reg == 0x%02x\n", __func__, ret, reg);
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ret = -EREMOTEIO;
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}
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}
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error:
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kfree(buf);
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return ret;
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}
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static int ds3000_readreg(struct ds3000_state *state, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{
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.addr = state->config->demod_address,
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.flags = 0,
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.buf = b0,
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.len = 1
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}, {
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.addr = state->config->demod_address,
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.flags = I2C_M_RD,
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.buf = b1,
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.len = 1
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}
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};
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2) {
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printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
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return ret;
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}
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dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
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return b1[0];
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}
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static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{
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.addr = 0x60,
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.flags = 0,
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.buf = b0,
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.len = 1
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}, {
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.addr = 0x60,
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.flags = I2C_M_RD,
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.buf = b1,
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.len = 1
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}
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};
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ds3000_writereg(state, 0x03, 0x12);
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2) {
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printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
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return ret;
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}
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dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
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return b1[0];
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}
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static int ds3000_load_firmware(struct dvb_frontend *fe,
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const struct firmware *fw);
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static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
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{
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struct ds3000_state *state = fe->demodulator_priv;
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const struct firmware *fw;
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int ret = 0;
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dprintk("%s()\n", __func__);
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if (ds3000_readreg(state, 0xb2) <= 0)
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return ret;
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if (state->skip_fw_load)
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return 0;
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/* Load firmware */
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/* request the firmware, this will block until someone uploads it */
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printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
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DS3000_DEFAULT_FIRMWARE);
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ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
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state->i2c->dev.parent);
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printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
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if (ret) {
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printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
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"found?)\n", __func__);
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return ret;
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}
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/* Make sure we don't recurse back through here during loading */
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state->skip_fw_load = 1;
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ret = ds3000_load_firmware(fe, fw);
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if (ret)
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printk("%s: Writing firmware to device failed\n", __func__);
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release_firmware(fw);
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dprintk("%s: Firmware upload %s\n", __func__,
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ret == 0 ? "complete" : "failed");
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/* Ensure firmware is always loaded if required */
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state->skip_fw_load = 0;
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return ret;
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}
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static int ds3000_load_firmware(struct dvb_frontend *fe,
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const struct firmware *fw)
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{
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struct ds3000_state *state = fe->demodulator_priv;
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dprintk("%s\n", __func__);
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dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
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fw->size,
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fw->data[0],
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fw->data[1],
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fw->data[fw->size - 2],
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fw->data[fw->size - 1]);
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/* Begin the firmware load process */
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ds3000_writereg(state, 0xb2, 0x01);
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/* write the entire firmware */
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ds3000_writeFW(state, 0xb0, fw->data, fw->size);
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ds3000_writereg(state, 0xb2, 0x00);
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return 0;
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}
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static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
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{
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struct ds3000_state *state = fe->demodulator_priv;
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u8 data;
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dprintk("%s(%d)\n", __func__, voltage);
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data = ds3000_readreg(state, 0xa2);
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data |= 0x03; /* bit0 V/H, bit1 off/on */
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switch (voltage) {
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case SEC_VOLTAGE_18:
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data &= ~0x03;
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break;
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case SEC_VOLTAGE_13:
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data &= ~0x03;
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data |= 0x01;
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break;
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case SEC_VOLTAGE_OFF:
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break;
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}
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ds3000_writereg(state, 0xa2, data);
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return 0;
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}
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static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
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{
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struct ds3000_state *state = fe->demodulator_priv;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int lock;
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*status = 0;
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switch (c->delivery_system) {
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case SYS_DVBS:
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lock = ds3000_readreg(state, 0xd1);
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if ((lock & 0x07) == 0x07)
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC |
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FE_HAS_LOCK;
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break;
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case SYS_DVBS2:
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lock = ds3000_readreg(state, 0x0d);
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if ((lock & 0x8f) == 0x8f)
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC |
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FE_HAS_LOCK;
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break;
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default:
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return 1;
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}
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|
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dprintk("%s: status = 0x%02x\n", __func__, lock);
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|
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return 0;
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}
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|
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/* read DS3000 BER value */
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static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
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{
|
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struct ds3000_state *state = fe->demodulator_priv;
|
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
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u8 data;
|
|
u32 ber_reading, lpdc_frames;
|
|
|
|
dprintk("%s()\n", __func__);
|
|
|
|
switch (c->delivery_system) {
|
|
case SYS_DVBS:
|
|
/* set the number of bytes checked during
|
|
BER estimation */
|
|
ds3000_writereg(state, 0xf9, 0x04);
|
|
/* read BER estimation status */
|
|
data = ds3000_readreg(state, 0xf8);
|
|
/* check if BER estimation is ready */
|
|
if ((data & 0x10) == 0) {
|
|
/* this is the number of error bits,
|
|
to calculate the bit error rate
|
|
divide to 8388608 */
|
|
*ber = (ds3000_readreg(state, 0xf7) << 8) |
|
|
ds3000_readreg(state, 0xf6);
|
|
/* start counting error bits */
|
|
/* need to be set twice
|
|
otherwise it fails sometimes */
|
|
data |= 0x10;
|
|
ds3000_writereg(state, 0xf8, data);
|
|
ds3000_writereg(state, 0xf8, data);
|
|
} else
|
|
/* used to indicate that BER estimation
|
|
is not ready, i.e. BER is unknown */
|
|
*ber = 0xffffffff;
|
|
break;
|
|
case SYS_DVBS2:
|
|
/* read the number of LPDC decoded frames */
|
|
lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
|
|
(ds3000_readreg(state, 0xd6) << 8) |
|
|
ds3000_readreg(state, 0xd5);
|
|
/* read the number of packets with bad CRC */
|
|
ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
|
|
ds3000_readreg(state, 0xf7);
|
|
if (lpdc_frames > 750) {
|
|
/* clear LPDC frame counters */
|
|
ds3000_writereg(state, 0xd1, 0x01);
|
|
/* clear bad packets counter */
|
|
ds3000_writereg(state, 0xf9, 0x01);
|
|
/* enable bad packets counter */
|
|
ds3000_writereg(state, 0xf9, 0x00);
|
|
/* enable LPDC frame counters */
|
|
ds3000_writereg(state, 0xd1, 0x00);
|
|
*ber = ber_reading;
|
|
} else
|
|
/* used to indicate that BER estimation is not ready,
|
|
i.e. BER is unknown */
|
|
*ber = 0xffffffff;
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* read TS2020 signal strength */
|
|
static int ds3000_read_signal_strength(struct dvb_frontend *fe,
|
|
u16 *signal_strength)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
u16 sig_reading, sig_strength;
|
|
u8 rfgain, bbgain;
|
|
|
|
dprintk("%s()\n", __func__);
|
|
|
|
rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
|
|
bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
|
|
|
|
if (rfgain > 15)
|
|
rfgain = 15;
|
|
if (bbgain > 13)
|
|
bbgain = 13;
|
|
|
|
sig_reading = rfgain * 2 + bbgain * 3;
|
|
|
|
sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
|
|
|
|
/* cook the value to be suitable for szap-s2 human readable output */
|
|
*signal_strength = sig_strength * 1000;
|
|
|
|
dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
|
|
sig_reading, *signal_strength);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* calculate DS3000 snr value in dB */
|
|
static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
|
u8 snr_reading, snr_value;
|
|
u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
|
|
static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
|
|
0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
|
|
0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
|
|
0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
|
|
};
|
|
static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
|
|
0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
|
|
0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
|
|
0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
|
|
0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
|
|
0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
|
|
0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
|
|
0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
|
|
0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
|
|
0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
|
|
0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
|
|
0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
|
|
0x49e9, 0x4a20, 0x4a57
|
|
};
|
|
|
|
dprintk("%s()\n", __func__);
|
|
|
|
switch (c->delivery_system) {
|
|
case SYS_DVBS:
|
|
snr_reading = ds3000_readreg(state, 0xff);
|
|
snr_reading /= 8;
|
|
if (snr_reading == 0)
|
|
*snr = 0x0000;
|
|
else {
|
|
if (snr_reading > 20)
|
|
snr_reading = 20;
|
|
snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
|
|
/* cook the value to be suitable for szap-s2
|
|
human readable output */
|
|
*snr = snr_value * 8 * 655;
|
|
}
|
|
dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
|
|
snr_reading, *snr);
|
|
break;
|
|
case SYS_DVBS2:
|
|
dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
|
|
(ds3000_readreg(state, 0x8d) << 4);
|
|
dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
|
|
tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
|
|
if (tmp == 0) {
|
|
*snr = 0x0000;
|
|
return 0;
|
|
}
|
|
if (dvbs2_noise_reading == 0) {
|
|
snr_value = 0x0013;
|
|
/* cook the value to be suitable for szap-s2
|
|
human readable output */
|
|
*snr = 0xffff;
|
|
return 0;
|
|
}
|
|
if (tmp > dvbs2_noise_reading) {
|
|
snr_reading = tmp / dvbs2_noise_reading;
|
|
if (snr_reading > 80)
|
|
snr_reading = 80;
|
|
snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
|
|
/* cook the value to be suitable for szap-s2
|
|
human readable output */
|
|
*snr = snr_value * 5 * 655;
|
|
} else {
|
|
snr_reading = dvbs2_noise_reading / tmp;
|
|
if (snr_reading > 80)
|
|
snr_reading = 80;
|
|
*snr = -(dvbs2_snr_tab[snr_reading] / 1000);
|
|
}
|
|
dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
|
|
snr_reading, *snr);
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* read DS3000 uncorrected blocks */
|
|
static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
|
u8 data;
|
|
u16 _ucblocks;
|
|
|
|
dprintk("%s()\n", __func__);
|
|
|
|
switch (c->delivery_system) {
|
|
case SYS_DVBS:
|
|
*ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
|
|
ds3000_readreg(state, 0xf4);
|
|
data = ds3000_readreg(state, 0xf8);
|
|
/* clear packet counters */
|
|
data &= ~0x20;
|
|
ds3000_writereg(state, 0xf8, data);
|
|
/* enable packet counters */
|
|
data |= 0x20;
|
|
ds3000_writereg(state, 0xf8, data);
|
|
break;
|
|
case SYS_DVBS2:
|
|
_ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
|
|
ds3000_readreg(state, 0xe1);
|
|
if (_ucblocks > state->prevUCBS2)
|
|
*ucblocks = _ucblocks - state->prevUCBS2;
|
|
else
|
|
*ucblocks = state->prevUCBS2 - _ucblocks;
|
|
state->prevUCBS2 = _ucblocks;
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
u8 data;
|
|
|
|
dprintk("%s(%d)\n", __func__, tone);
|
|
if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
|
|
printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
|
|
return -EINVAL;
|
|
}
|
|
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data &= ~0xc0;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
|
|
switch (tone) {
|
|
case SEC_TONE_ON:
|
|
dprintk("%s: setting tone on\n", __func__);
|
|
data = ds3000_readreg(state, 0xa1);
|
|
data &= ~0x43;
|
|
data |= 0x04;
|
|
ds3000_writereg(state, 0xa1, data);
|
|
break;
|
|
case SEC_TONE_OFF:
|
|
dprintk("%s: setting tone off\n", __func__);
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data |= 0x80;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
|
|
struct dvb_diseqc_master_cmd *d)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
int i;
|
|
u8 data;
|
|
|
|
/* Dump DiSEqC message */
|
|
dprintk("%s(", __func__);
|
|
for (i = 0 ; i < d->msg_len;) {
|
|
dprintk("0x%02x", d->msg[i]);
|
|
if (++i < d->msg_len)
|
|
dprintk(", ");
|
|
}
|
|
|
|
/* enable DiSEqC message send pin */
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data &= ~0xc0;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
|
|
/* DiSEqC message */
|
|
for (i = 0; i < d->msg_len; i++)
|
|
ds3000_writereg(state, 0xa3 + i, d->msg[i]);
|
|
|
|
data = ds3000_readreg(state, 0xa1);
|
|
/* clear DiSEqC message length and status,
|
|
enable DiSEqC message send */
|
|
data &= ~0xf8;
|
|
/* set DiSEqC mode, modulation active during 33 pulses,
|
|
set DiSEqC message length */
|
|
data |= ((d->msg_len - 1) << 3) | 0x07;
|
|
ds3000_writereg(state, 0xa1, data);
|
|
|
|
/* wait up to 150ms for DiSEqC transmission to complete */
|
|
for (i = 0; i < 15; i++) {
|
|
data = ds3000_readreg(state, 0xa1);
|
|
if ((data & 0x40) == 0)
|
|
break;
|
|
msleep(10);
|
|
}
|
|
|
|
/* DiSEqC timeout after 150ms */
|
|
if (i == 15) {
|
|
data = ds3000_readreg(state, 0xa1);
|
|
data &= ~0x80;
|
|
data |= 0x40;
|
|
ds3000_writereg(state, 0xa1, data);
|
|
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data &= ~0xc0;
|
|
data |= 0x80;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
|
|
return 1;
|
|
}
|
|
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data &= ~0xc0;
|
|
data |= 0x80;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Send DiSEqC burst */
|
|
static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
|
|
fe_sec_mini_cmd_t burst)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
int i;
|
|
u8 data;
|
|
|
|
dprintk("%s()\n", __func__);
|
|
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data &= ~0xc0;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
|
|
/* DiSEqC burst */
|
|
if (burst == SEC_MINI_A)
|
|
/* Unmodulated tone burst */
|
|
ds3000_writereg(state, 0xa1, 0x02);
|
|
else if (burst == SEC_MINI_B)
|
|
/* Modulated tone burst */
|
|
ds3000_writereg(state, 0xa1, 0x01);
|
|
else
|
|
return -EINVAL;
|
|
|
|
msleep(13);
|
|
for (i = 0; i < 5; i++) {
|
|
data = ds3000_readreg(state, 0xa1);
|
|
if ((data & 0x40) == 0)
|
|
break;
|
|
msleep(1);
|
|
}
|
|
|
|
if (i == 5) {
|
|
data = ds3000_readreg(state, 0xa1);
|
|
data &= ~0x80;
|
|
data |= 0x40;
|
|
ds3000_writereg(state, 0xa1, data);
|
|
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data &= ~0xc0;
|
|
data |= 0x80;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
|
|
return 1;
|
|
}
|
|
|
|
data = ds3000_readreg(state, 0xa2);
|
|
data &= ~0xc0;
|
|
data |= 0x80;
|
|
ds3000_writereg(state, 0xa2, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ds3000_release(struct dvb_frontend *fe)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
dprintk("%s\n", __func__);
|
|
kfree(state);
|
|
}
|
|
|
|
static struct dvb_frontend_ops ds3000_ops;
|
|
|
|
struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
|
|
struct i2c_adapter *i2c)
|
|
{
|
|
struct ds3000_state *state = NULL;
|
|
int ret;
|
|
|
|
dprintk("%s\n", __func__);
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
|
|
if (state == NULL) {
|
|
printk(KERN_ERR "Unable to kmalloc\n");
|
|
goto error2;
|
|
}
|
|
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
state->prevUCBS2 = 0;
|
|
|
|
/* check if the demod is present */
|
|
ret = ds3000_readreg(state, 0x00) & 0xfe;
|
|
if (ret != 0xe0) {
|
|
printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
|
|
goto error3;
|
|
}
|
|
|
|
printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
|
|
ds3000_readreg(state, 0x02),
|
|
ds3000_readreg(state, 0x01));
|
|
|
|
memcpy(&state->frontend.ops, &ds3000_ops,
|
|
sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
return &state->frontend;
|
|
|
|
error3:
|
|
kfree(state);
|
|
error2:
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(ds3000_attach);
|
|
|
|
static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
|
|
s32 carrier_offset_khz)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
s32 tmp;
|
|
|
|
tmp = carrier_offset_khz;
|
|
tmp *= 65536;
|
|
tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
|
|
|
|
if (tmp < 0)
|
|
tmp += 65536;
|
|
|
|
ds3000_writereg(state, 0x5f, tmp >> 8);
|
|
ds3000_writereg(state, 0x5e, tmp & 0xff);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ds3000_set_frontend(struct dvb_frontend *fe)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
|
|
|
int i;
|
|
fe_status_t status;
|
|
u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
|
|
s32 offset_khz;
|
|
u16 value, ndiv;
|
|
u32 f3db;
|
|
|
|
dprintk("%s() ", __func__);
|
|
|
|
if (state->config->set_ts_params)
|
|
state->config->set_ts_params(fe, 0);
|
|
/* Tune */
|
|
/* unknown */
|
|
ds3000_tuner_writereg(state, 0x07, 0x02);
|
|
ds3000_tuner_writereg(state, 0x10, 0x00);
|
|
ds3000_tuner_writereg(state, 0x60, 0x79);
|
|
ds3000_tuner_writereg(state, 0x08, 0x01);
|
|
ds3000_tuner_writereg(state, 0x00, 0x01);
|
|
div4 = 0;
|
|
|
|
/* calculate and set freq divider */
|
|
if (c->frequency < 1146000) {
|
|
ds3000_tuner_writereg(state, 0x10, 0x11);
|
|
div4 = 1;
|
|
ndiv = ((c->frequency * (6 + 8) * 4) +
|
|
(DS3000_XTAL_FREQ / 2)) /
|
|
DS3000_XTAL_FREQ - 1024;
|
|
} else {
|
|
ds3000_tuner_writereg(state, 0x10, 0x01);
|
|
ndiv = ((c->frequency * (6 + 8) * 2) +
|
|
(DS3000_XTAL_FREQ / 2)) /
|
|
DS3000_XTAL_FREQ - 1024;
|
|
}
|
|
|
|
ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
|
|
ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
|
|
|
|
/* set pll */
|
|
ds3000_tuner_writereg(state, 0x03, 0x06);
|
|
ds3000_tuner_writereg(state, 0x51, 0x0f);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1f);
|
|
ds3000_tuner_writereg(state, 0x50, 0x10);
|
|
ds3000_tuner_writereg(state, 0x50, 0x00);
|
|
msleep(5);
|
|
|
|
/* unknown */
|
|
ds3000_tuner_writereg(state, 0x51, 0x17);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1f);
|
|
ds3000_tuner_writereg(state, 0x50, 0x08);
|
|
ds3000_tuner_writereg(state, 0x50, 0x00);
|
|
msleep(5);
|
|
|
|
value = ds3000_tuner_readreg(state, 0x3d);
|
|
value &= 0x0f;
|
|
if ((value > 4) && (value < 15)) {
|
|
value -= 3;
|
|
if (value < 4)
|
|
value = 4;
|
|
value = ((value << 3) | 0x01) & 0x79;
|
|
}
|
|
|
|
ds3000_tuner_writereg(state, 0x60, value);
|
|
ds3000_tuner_writereg(state, 0x51, 0x17);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1f);
|
|
ds3000_tuner_writereg(state, 0x50, 0x08);
|
|
ds3000_tuner_writereg(state, 0x50, 0x00);
|
|
|
|
/* set low-pass filter period */
|
|
ds3000_tuner_writereg(state, 0x04, 0x2e);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1b);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1f);
|
|
ds3000_tuner_writereg(state, 0x50, 0x04);
|
|
ds3000_tuner_writereg(state, 0x50, 0x00);
|
|
msleep(5);
|
|
|
|
f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
|
|
if ((c->symbol_rate / 1000) < 5000)
|
|
f3db += 3000;
|
|
if (f3db < 7000)
|
|
f3db = 7000;
|
|
if (f3db > 40000)
|
|
f3db = 40000;
|
|
|
|
/* set low-pass filter baseband */
|
|
value = ds3000_tuner_readreg(state, 0x26);
|
|
mlpf = 0x2e * 207 / ((value << 1) + 151);
|
|
mlpf_max = mlpf * 135 / 100;
|
|
mlpf_min = mlpf * 78 / 100;
|
|
if (mlpf_max > 63)
|
|
mlpf_max = 63;
|
|
|
|
/* rounded to the closest integer */
|
|
nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
|
|
/ (2766 * DS3000_XTAL_FREQ);
|
|
if (nlpf > 23)
|
|
nlpf = 23;
|
|
if (nlpf < 1)
|
|
nlpf = 1;
|
|
|
|
/* rounded to the closest integer */
|
|
mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
|
|
(1000 * f3db / 2)) / (1000 * f3db);
|
|
|
|
if (mlpf_new < mlpf_min) {
|
|
nlpf++;
|
|
mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
|
|
(1000 * f3db / 2)) / (1000 * f3db);
|
|
}
|
|
|
|
if (mlpf_new > mlpf_max)
|
|
mlpf_new = mlpf_max;
|
|
|
|
ds3000_tuner_writereg(state, 0x04, mlpf_new);
|
|
ds3000_tuner_writereg(state, 0x06, nlpf);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1b);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1f);
|
|
ds3000_tuner_writereg(state, 0x50, 0x04);
|
|
ds3000_tuner_writereg(state, 0x50, 0x00);
|
|
msleep(5);
|
|
|
|
/* unknown */
|
|
ds3000_tuner_writereg(state, 0x51, 0x1e);
|
|
ds3000_tuner_writereg(state, 0x51, 0x1f);
|
|
ds3000_tuner_writereg(state, 0x50, 0x01);
|
|
ds3000_tuner_writereg(state, 0x50, 0x00);
|
|
msleep(60);
|
|
|
|
offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
|
|
/ (6 + 8) / (div4 + 1) / 2 - c->frequency;
|
|
|
|
/* ds3000 global reset */
|
|
ds3000_writereg(state, 0x07, 0x80);
|
|
ds3000_writereg(state, 0x07, 0x00);
|
|
/* ds3000 build-in uC reset */
|
|
ds3000_writereg(state, 0xb2, 0x01);
|
|
/* ds3000 software reset */
|
|
ds3000_writereg(state, 0x00, 0x01);
|
|
|
|
switch (c->delivery_system) {
|
|
case SYS_DVBS:
|
|
/* initialise the demod in DVB-S mode */
|
|
for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
|
|
ds3000_writereg(state,
|
|
ds3000_dvbs_init_tab[i],
|
|
ds3000_dvbs_init_tab[i + 1]);
|
|
value = ds3000_readreg(state, 0xfe);
|
|
value &= 0xc0;
|
|
value |= 0x1b;
|
|
ds3000_writereg(state, 0xfe, value);
|
|
break;
|
|
case SYS_DVBS2:
|
|
/* initialise the demod in DVB-S2 mode */
|
|
for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
|
|
ds3000_writereg(state,
|
|
ds3000_dvbs2_init_tab[i],
|
|
ds3000_dvbs2_init_tab[i + 1]);
|
|
if (c->symbol_rate >= 30000000)
|
|
ds3000_writereg(state, 0xfe, 0x54);
|
|
else
|
|
ds3000_writereg(state, 0xfe, 0x98);
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
|
|
/* enable 27MHz clock output */
|
|
ds3000_writereg(state, 0x29, 0x80);
|
|
/* enable ac coupling */
|
|
ds3000_writereg(state, 0x25, 0x8a);
|
|
|
|
/* enhance symbol rate performance */
|
|
if ((c->symbol_rate / 1000) <= 5000) {
|
|
value = 29777 / (c->symbol_rate / 1000) + 1;
|
|
if (value % 2 != 0)
|
|
value++;
|
|
ds3000_writereg(state, 0xc3, 0x0d);
|
|
ds3000_writereg(state, 0xc8, value);
|
|
ds3000_writereg(state, 0xc4, 0x10);
|
|
ds3000_writereg(state, 0xc7, 0x0e);
|
|
} else if ((c->symbol_rate / 1000) <= 10000) {
|
|
value = 92166 / (c->symbol_rate / 1000) + 1;
|
|
if (value % 2 != 0)
|
|
value++;
|
|
ds3000_writereg(state, 0xc3, 0x07);
|
|
ds3000_writereg(state, 0xc8, value);
|
|
ds3000_writereg(state, 0xc4, 0x09);
|
|
ds3000_writereg(state, 0xc7, 0x12);
|
|
} else if ((c->symbol_rate / 1000) <= 20000) {
|
|
value = 64516 / (c->symbol_rate / 1000) + 1;
|
|
ds3000_writereg(state, 0xc3, value);
|
|
ds3000_writereg(state, 0xc8, 0x0e);
|
|
ds3000_writereg(state, 0xc4, 0x07);
|
|
ds3000_writereg(state, 0xc7, 0x18);
|
|
} else {
|
|
value = 129032 / (c->symbol_rate / 1000) + 1;
|
|
ds3000_writereg(state, 0xc3, value);
|
|
ds3000_writereg(state, 0xc8, 0x0a);
|
|
ds3000_writereg(state, 0xc4, 0x05);
|
|
ds3000_writereg(state, 0xc7, 0x24);
|
|
}
|
|
|
|
/* normalized symbol rate rounded to the closest integer */
|
|
value = (((c->symbol_rate / 1000) << 16) +
|
|
(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
|
|
ds3000_writereg(state, 0x61, value & 0x00ff);
|
|
ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
|
|
|
|
/* co-channel interference cancellation disabled */
|
|
ds3000_writereg(state, 0x56, 0x00);
|
|
|
|
/* equalizer disabled */
|
|
ds3000_writereg(state, 0x76, 0x00);
|
|
|
|
/*ds3000_writereg(state, 0x08, 0x03);
|
|
ds3000_writereg(state, 0xfd, 0x22);
|
|
ds3000_writereg(state, 0x08, 0x07);
|
|
ds3000_writereg(state, 0xfd, 0x42);
|
|
ds3000_writereg(state, 0x08, 0x07);*/
|
|
|
|
if (state->config->ci_mode) {
|
|
switch (c->delivery_system) {
|
|
case SYS_DVBS:
|
|
default:
|
|
ds3000_writereg(state, 0xfd, 0x80);
|
|
break;
|
|
case SYS_DVBS2:
|
|
ds3000_writereg(state, 0xfd, 0x01);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* ds3000 out of software reset */
|
|
ds3000_writereg(state, 0x00, 0x00);
|
|
/* start ds3000 build-in uC */
|
|
ds3000_writereg(state, 0xb2, 0x00);
|
|
|
|
ds3000_set_carrier_offset(fe, offset_khz);
|
|
|
|
for (i = 0; i < 30 ; i++) {
|
|
ds3000_read_status(fe, &status);
|
|
if (status & FE_HAS_LOCK)
|
|
break;
|
|
|
|
msleep(10);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ds3000_tune(struct dvb_frontend *fe,
|
|
bool re_tune,
|
|
unsigned int mode_flags,
|
|
unsigned int *delay,
|
|
fe_status_t *status)
|
|
{
|
|
if (re_tune) {
|
|
int ret = ds3000_set_frontend(fe);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
*delay = HZ / 5;
|
|
|
|
return ds3000_read_status(fe, status);
|
|
}
|
|
|
|
static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
|
|
{
|
|
dprintk("%s()\n", __func__);
|
|
return DVBFE_ALGO_HW;
|
|
}
|
|
|
|
/*
|
|
* Initialise or wake up device
|
|
*
|
|
* Power config will reset and load initial firmware if required
|
|
*/
|
|
static int ds3000_initfe(struct dvb_frontend *fe)
|
|
{
|
|
struct ds3000_state *state = fe->demodulator_priv;
|
|
int ret;
|
|
|
|
dprintk("%s()\n", __func__);
|
|
/* hard reset */
|
|
ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
|
|
msleep(1);
|
|
|
|
/* TS2020 init */
|
|
ds3000_tuner_writereg(state, 0x42, 0x73);
|
|
ds3000_tuner_writereg(state, 0x05, 0x01);
|
|
ds3000_tuner_writereg(state, 0x62, 0xf5);
|
|
/* Load the firmware if required */
|
|
ret = ds3000_firmware_ondemand(fe);
|
|
if (ret != 0) {
|
|
printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Put device to sleep */
|
|
static int ds3000_sleep(struct dvb_frontend *fe)
|
|
{
|
|
dprintk("%s()\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static struct dvb_frontend_ops ds3000_ops = {
|
|
.delsys = { SYS_DVBS, SYS_DVBS2},
|
|
.info = {
|
|
.name = "Montage Technology DS3000/TS2020",
|
|
.frequency_min = 950000,
|
|
.frequency_max = 2150000,
|
|
.frequency_stepsize = 1011, /* kHz for QPSK frontends */
|
|
.frequency_tolerance = 5000,
|
|
.symbol_rate_min = 1000000,
|
|
.symbol_rate_max = 45000000,
|
|
.caps = FE_CAN_INVERSION_AUTO |
|
|
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
|
|
FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
|
FE_CAN_2G_MODULATION |
|
|
FE_CAN_QPSK | FE_CAN_RECOVER
|
|
},
|
|
|
|
.release = ds3000_release,
|
|
|
|
.init = ds3000_initfe,
|
|
.sleep = ds3000_sleep,
|
|
.read_status = ds3000_read_status,
|
|
.read_ber = ds3000_read_ber,
|
|
.read_signal_strength = ds3000_read_signal_strength,
|
|
.read_snr = ds3000_read_snr,
|
|
.read_ucblocks = ds3000_read_ucblocks,
|
|
.set_voltage = ds3000_set_voltage,
|
|
.set_tone = ds3000_set_tone,
|
|
.diseqc_send_master_cmd = ds3000_send_diseqc_msg,
|
|
.diseqc_send_burst = ds3000_diseqc_send_burst,
|
|
.get_frontend_algo = ds3000_get_algo,
|
|
|
|
.set_frontend = ds3000_set_frontend,
|
|
.tune = ds3000_tune,
|
|
};
|
|
|
|
module_param(debug, int, 0644);
|
|
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
|
|
|
|
MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
|
|
"DS3000/TS2020 hardware");
|
|
MODULE_AUTHOR("Konstantin Dimitrov");
|
|
MODULE_LICENSE("GPL");
|