799 lines
18 KiB
C
799 lines
18 KiB
C
/*
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Driver for STV0297 demodulator
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Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
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Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include "dvb_frontend.h"
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#include "stv0297.h"
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struct stv0297_state {
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struct i2c_adapter *i2c;
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struct dvb_frontend_ops ops;
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const struct stv0297_config *config;
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struct dvb_frontend frontend;
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unsigned long base_freq;
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u8 pwm;
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};
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#if 1
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#define dprintk(x...) printk(x)
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#else
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#define dprintk(x...)
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#endif
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#define STV0297_CLOCK_KHZ 28900
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static u8 init_tab[] = {
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0x00, 0x09,
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0x01, 0x69,
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0x03, 0x00,
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0x04, 0x00,
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0x07, 0x00,
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0x08, 0x00,
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0x20, 0x00,
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0x21, 0x40,
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0x22, 0x00,
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0x23, 0x00,
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0x24, 0x40,
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0x25, 0x88,
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0x30, 0xff,
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0x31, 0x00,
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0x32, 0xff,
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0x33, 0x00,
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0x34, 0x50,
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0x35, 0x7f,
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0x36, 0x00,
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0x37, 0x20,
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0x38, 0x00,
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0x40, 0x1c,
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0x41, 0xff,
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0x42, 0x29,
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0x43, 0x00,
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0x44, 0xff,
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0x45, 0x00,
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0x46, 0x00,
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0x49, 0x04,
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0x4a, 0xff,
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0x4b, 0x7f,
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0x52, 0x30,
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0x55, 0xae,
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0x56, 0x47,
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0x57, 0xe1,
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0x58, 0x3a,
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0x5a, 0x1e,
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0x5b, 0x34,
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0x60, 0x00,
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0x63, 0x00,
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0x64, 0x00,
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0x65, 0x00,
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0x66, 0x00,
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0x67, 0x00,
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0x68, 0x00,
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0x69, 0x00,
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0x6a, 0x02,
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0x6b, 0x00,
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0x70, 0xff,
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0x71, 0x00,
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0x72, 0x00,
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0x73, 0x00,
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0x74, 0x0c,
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0x80, 0x00,
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0x81, 0x00,
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0x82, 0x00,
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0x83, 0x00,
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0x84, 0x04,
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0x85, 0x80,
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0x86, 0x24,
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0x87, 0x78,
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0x88, 0x00,
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0x89, 0x00,
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0x90, 0x01,
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0x91, 0x01,
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0xa0, 0x00,
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0xa1, 0x00,
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0xa2, 0x00,
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0xb0, 0x91,
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0xb1, 0x0b,
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0xc0, 0x53,
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0xc1, 0x70,
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0xc2, 0x12,
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0xd0, 0x00,
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0xd1, 0x00,
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0xd2, 0x00,
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0xd3, 0x00,
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0xd4, 0x00,
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0xd5, 0x00,
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0xde, 0x00,
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0xdf, 0x00,
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0x61, 0x49,
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0x62, 0x0b,
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0x53, 0x08,
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0x59, 0x08,
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};
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static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
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{
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int ret;
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u8 buf[] = { reg, data };
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struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
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"ret == %i)\n", __FUNCTION__, reg, data, ret);
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return (ret != 1) ? -1 : 0;
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}
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static int stv0297_readreg(struct stv0297_state *state, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len =
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1},
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{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
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};
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// this device needs a STOP between the register and data
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if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
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dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
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return -1;
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}
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if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
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dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
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return -1;
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}
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return b1[0];
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}
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static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
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{
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int val;
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val = stv0297_readreg(state, reg);
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val &= ~mask;
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val |= (data & mask);
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stv0297_writereg(state, reg, val);
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return 0;
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}
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static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
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{
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int ret;
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struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
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®1,.len = 1},
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{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
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};
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// this device needs a STOP between the register and data
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if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
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dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
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return -1;
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}
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if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
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dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
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return -1;
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}
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return 0;
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}
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static u32 stv0297_get_symbolrate(struct stv0297_state *state)
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{
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u64 tmp;
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tmp = stv0297_readreg(state, 0x55);
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tmp |= stv0297_readreg(state, 0x56) << 8;
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tmp |= stv0297_readreg(state, 0x57) << 16;
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tmp |= stv0297_readreg(state, 0x58) << 24;
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tmp *= STV0297_CLOCK_KHZ;
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tmp >>= 32;
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return (u32) tmp;
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}
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static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
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{
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long tmp;
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tmp = 131072L * srate; /* 131072 = 2^17 */
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tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */
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tmp = tmp * 8192L; /* 8192 = 2^13 */
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stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
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stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
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stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
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stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
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}
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static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
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{
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long tmp;
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tmp = (long) fshift *262144L; /* 262144 = 2*18 */
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tmp /= symrate;
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tmp *= 1024; /* 1024 = 2*10 */
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// adjust
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if (tmp >= 0) {
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tmp += 500000;
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} else {
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tmp -= 500000;
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}
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tmp /= 1000000;
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stv0297_writereg(state, 0x60, tmp & 0xFF);
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stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
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}
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static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
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{
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long tmp;
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/* symrate is hardcoded to 10000 */
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tmp = offset * 26844L; /* (2**28)/10000 */
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if (tmp < 0)
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tmp += 0x10000000;
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tmp &= 0x0FFFFFFF;
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stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
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stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
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stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
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stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
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}
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/*
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static long stv0297_get_carrieroffset(struct stv0297_state *state)
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{
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s64 tmp;
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stv0297_writereg(state, 0x6B, 0x00);
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tmp = stv0297_readreg(state, 0x66);
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tmp |= (stv0297_readreg(state, 0x67) << 8);
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tmp |= (stv0297_readreg(state, 0x68) << 16);
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tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
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tmp *= stv0297_get_symbolrate(state);
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tmp >>= 28;
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return (s32) tmp;
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}
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*/
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static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
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{
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s32 tmp;
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if (freq > 10000)
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freq -= STV0297_CLOCK_KHZ;
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tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
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tmp = (freq * 1000) / tmp;
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if (tmp > 0xffff)
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tmp = 0xffff;
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stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
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stv0297_writereg(state, 0x21, tmp >> 8);
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stv0297_writereg(state, 0x20, tmp);
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}
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static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
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{
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int val = 0;
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switch (modulation) {
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case QAM_16:
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val = 0;
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break;
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case QAM_32:
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val = 1;
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break;
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case QAM_64:
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val = 4;
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break;
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case QAM_128:
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val = 2;
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break;
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case QAM_256:
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val = 3;
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break;
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default:
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return -EINVAL;
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}
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stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
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return 0;
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}
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static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
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{
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int val = 0;
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switch (inversion) {
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case INVERSION_OFF:
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val = 0;
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break;
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case INVERSION_ON:
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val = 1;
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break;
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default:
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return -EINVAL;
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}
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stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
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return 0;
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}
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int stv0297_enable_plli2c(struct dvb_frontend *fe)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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stv0297_writereg(state, 0x87, 0x78);
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stv0297_writereg(state, 0x86, 0xc8);
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return 0;
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}
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static int stv0297_init(struct dvb_frontend *fe)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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int i;
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/* soft reset */
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stv0297_writereg_mask(state, 0x80, 1, 1);
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stv0297_writereg_mask(state, 0x80, 1, 0);
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/* reset deinterleaver */
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stv0297_writereg_mask(state, 0x81, 1, 1);
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stv0297_writereg_mask(state, 0x81, 1, 0);
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/* load init table */
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for (i = 0; i < sizeof(init_tab); i += 2) {
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stv0297_writereg(state, init_tab[i], init_tab[i + 1]);
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}
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/* set a dummy symbol rate */
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stv0297_set_symbolrate(state, 6900);
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/* invert AGC1 polarity */
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stv0297_writereg_mask(state, 0x88, 0x10, 0x10);
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/* setup bit error counting */
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stv0297_writereg_mask(state, 0xA0, 0x80, 0x00);
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stv0297_writereg_mask(state, 0xA0, 0x10, 0x00);
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stv0297_writereg_mask(state, 0xA0, 0x08, 0x00);
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stv0297_writereg_mask(state, 0xA0, 0x07, 0x04);
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/* min + max PWM */
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stv0297_writereg(state, 0x4a, 0x00);
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stv0297_writereg(state, 0x4b, state->pwm);
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msleep(200);
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if (state->config->pll_init)
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state->config->pll_init(fe);
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return 0;
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}
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static int stv0297_sleep(struct dvb_frontend *fe)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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stv0297_writereg_mask(state, 0x80, 1, 1);
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return 0;
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}
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static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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u8 sync = stv0297_readreg(state, 0xDF);
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*status = 0;
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if (sync & 0x80)
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*status |=
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FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
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return 0;
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}
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static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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u8 BER[3];
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stv0297_writereg(state, 0xA0, 0x80); // Start Counting bit errors for 4096 Bytes
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mdelay(25); // Hopefully got 4096 Bytes
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stv0297_readregs(state, 0xA0, BER, 3);
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mdelay(25);
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*ber = (BER[2] << 8 | BER[1]) / (8 * 4096);
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return 0;
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}
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static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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u8 STRENGTH[2];
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stv0297_readregs(state, 0x41, STRENGTH, 2);
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*strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
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return 0;
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}
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static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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u8 SNR[2];
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stv0297_readregs(state, 0x07, SNR, 2);
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*snr = SNR[1] << 8 | SNR[0];
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return 0;
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}
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static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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*ucblocks = (stv0297_readreg(state, 0xD5) << 8)
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| stv0297_readreg(state, 0xD4);
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return 0;
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}
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static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
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{
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struct stv0297_state *state = fe->demodulator_priv;
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int u_threshold;
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int initial_u;
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int blind_u;
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int delay;
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int sweeprate;
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int carrieroffset;
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unsigned long starttime;
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unsigned long timeout;
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fe_spectral_inversion_t inversion;
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switch (p->u.qam.modulation) {
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case QAM_16:
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case QAM_32:
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case QAM_64:
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delay = 100;
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sweeprate = 1500;
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break;
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case QAM_128:
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delay = 150;
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sweeprate = 1000;
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break;
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case QAM_256:
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delay = 200;
|
|
sweeprate = 500;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
// determine inversion dependant parameters
|
|
inversion = p->inversion;
|
|
if (state->config->invert)
|
|
inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
|
|
carrieroffset = -330;
|
|
switch (inversion) {
|
|
case INVERSION_OFF:
|
|
break;
|
|
|
|
case INVERSION_ON:
|
|
sweeprate = -sweeprate;
|
|
carrieroffset = -carrieroffset;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
stv0297_init(fe);
|
|
state->config->pll_set(fe, p);
|
|
|
|
/* clear software interrupts */
|
|
stv0297_writereg(state, 0x82, 0x0);
|
|
|
|
/* set initial demodulation frequency */
|
|
stv0297_set_initialdemodfreq(state, 7250);
|
|
|
|
/* setup AGC */
|
|
stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
|
|
stv0297_writereg(state, 0x41, 0x00);
|
|
stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
|
|
stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
|
|
stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
|
|
stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
|
|
stv0297_writereg(state, 0x72, 0x00);
|
|
stv0297_writereg(state, 0x73, 0x00);
|
|
stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
|
|
stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
|
|
stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
|
|
|
|
/* setup STL */
|
|
stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
|
|
stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
|
|
stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
|
|
stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
|
|
stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
|
|
|
|
/* disable frequency sweep */
|
|
stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
|
|
|
|
/* reset deinterleaver */
|
|
stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
|
|
stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
|
|
|
|
/* ??? */
|
|
stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
|
|
stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
|
|
|
|
/* reset equaliser */
|
|
u_threshold = stv0297_readreg(state, 0x00) & 0xf;
|
|
initial_u = stv0297_readreg(state, 0x01) >> 4;
|
|
blind_u = stv0297_readreg(state, 0x01) & 0xf;
|
|
stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
|
|
stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
|
|
stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
|
|
stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
|
|
stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
|
|
|
|
/* data comes from internal A/D */
|
|
stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
|
|
|
|
/* clear phase registers */
|
|
stv0297_writereg(state, 0x63, 0x00);
|
|
stv0297_writereg(state, 0x64, 0x00);
|
|
stv0297_writereg(state, 0x65, 0x00);
|
|
stv0297_writereg(state, 0x66, 0x00);
|
|
stv0297_writereg(state, 0x67, 0x00);
|
|
stv0297_writereg(state, 0x68, 0x00);
|
|
stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
|
|
|
|
/* set parameters */
|
|
stv0297_set_qam(state, p->u.qam.modulation);
|
|
stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);
|
|
stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
|
|
stv0297_set_carrieroffset(state, carrieroffset);
|
|
stv0297_set_inversion(state, inversion);
|
|
|
|
/* kick off lock */
|
|
stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
|
|
stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
|
|
stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
|
|
stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
|
|
stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
|
|
stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
|
|
stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
|
|
stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
|
|
|
|
/* wait for WGAGC lock */
|
|
starttime = jiffies;
|
|
timeout = jiffies + msecs_to_jiffies(2000);
|
|
while (time_before(jiffies, timeout)) {
|
|
msleep(10);
|
|
if (stv0297_readreg(state, 0x43) & 0x08)
|
|
break;
|
|
}
|
|
if (time_after(jiffies, timeout)) {
|
|
goto timeout;
|
|
}
|
|
msleep(20);
|
|
|
|
/* wait for equaliser partial convergence */
|
|
timeout = jiffies + msecs_to_jiffies(500);
|
|
while (time_before(jiffies, timeout)) {
|
|
msleep(10);
|
|
|
|
if (stv0297_readreg(state, 0x82) & 0x04) {
|
|
break;
|
|
}
|
|
}
|
|
if (time_after(jiffies, timeout)) {
|
|
goto timeout;
|
|
}
|
|
|
|
/* wait for equaliser full convergence */
|
|
timeout = jiffies + msecs_to_jiffies(delay);
|
|
while (time_before(jiffies, timeout)) {
|
|
msleep(10);
|
|
|
|
if (stv0297_readreg(state, 0x82) & 0x08) {
|
|
break;
|
|
}
|
|
}
|
|
if (time_after(jiffies, timeout)) {
|
|
goto timeout;
|
|
}
|
|
|
|
/* disable sweep */
|
|
stv0297_writereg_mask(state, 0x6a, 1, 0);
|
|
stv0297_writereg_mask(state, 0x88, 8, 0);
|
|
|
|
/* wait for main lock */
|
|
timeout = jiffies + msecs_to_jiffies(20);
|
|
while (time_before(jiffies, timeout)) {
|
|
msleep(10);
|
|
|
|
if (stv0297_readreg(state, 0xDF) & 0x80) {
|
|
break;
|
|
}
|
|
}
|
|
if (time_after(jiffies, timeout)) {
|
|
goto timeout;
|
|
}
|
|
msleep(100);
|
|
|
|
/* is it still locked after that delay? */
|
|
if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
|
|
goto timeout;
|
|
}
|
|
|
|
/* success!! */
|
|
stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
|
|
state->base_freq = p->frequency;
|
|
return 0;
|
|
|
|
timeout:
|
|
stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
|
|
return 0;
|
|
}
|
|
|
|
static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
|
|
{
|
|
struct stv0297_state *state = fe->demodulator_priv;
|
|
int reg_00, reg_83;
|
|
|
|
reg_00 = stv0297_readreg(state, 0x00);
|
|
reg_83 = stv0297_readreg(state, 0x83);
|
|
|
|
p->frequency = state->base_freq;
|
|
p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
|
|
if (state->config->invert)
|
|
p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
|
|
p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
|
|
p->u.qam.fec_inner = FEC_NONE;
|
|
|
|
switch ((reg_00 >> 4) & 0x7) {
|
|
case 0:
|
|
p->u.qam.modulation = QAM_16;
|
|
break;
|
|
case 1:
|
|
p->u.qam.modulation = QAM_32;
|
|
break;
|
|
case 2:
|
|
p->u.qam.modulation = QAM_128;
|
|
break;
|
|
case 3:
|
|
p->u.qam.modulation = QAM_256;
|
|
break;
|
|
case 4:
|
|
p->u.qam.modulation = QAM_64;
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void stv0297_release(struct dvb_frontend *fe)
|
|
{
|
|
struct stv0297_state *state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static struct dvb_frontend_ops stv0297_ops;
|
|
|
|
struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
|
|
struct i2c_adapter *i2c, int pwm)
|
|
{
|
|
struct stv0297_state *state = NULL;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
goto error;
|
|
|
|
/* setup the state */
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
|
|
state->base_freq = 0;
|
|
state->pwm = pwm;
|
|
|
|
/* check if the demod is there */
|
|
if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
|
|
goto error;
|
|
|
|
/* create dvb_frontend */
|
|
state->frontend.ops = &state->ops;
|
|
state->frontend.demodulator_priv = state;
|
|
return &state->frontend;
|
|
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
|
|
static struct dvb_frontend_ops stv0297_ops = {
|
|
|
|
.info = {
|
|
.name = "ST STV0297 DVB-C",
|
|
.type = FE_QAM,
|
|
.frequency_min = 64000000,
|
|
.frequency_max = 1300000000,
|
|
.frequency_stepsize = 62500,
|
|
.symbol_rate_min = 870000,
|
|
.symbol_rate_max = 11700000,
|
|
.caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
|
|
FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
|
|
|
|
.release = stv0297_release,
|
|
|
|
.init = stv0297_init,
|
|
.sleep = stv0297_sleep,
|
|
|
|
.set_frontend = stv0297_set_frontend,
|
|
.get_frontend = stv0297_get_frontend,
|
|
|
|
.read_status = stv0297_read_status,
|
|
.read_ber = stv0297_read_ber,
|
|
.read_signal_strength = stv0297_read_signal_strength,
|
|
.read_snr = stv0297_read_snr,
|
|
.read_ucblocks = stv0297_read_ucblocks,
|
|
};
|
|
|
|
MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
|
|
MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
EXPORT_SYMBOL(stv0297_attach);
|
|
EXPORT_SYMBOL(stv0297_enable_plli2c);
|