496 lines
14 KiB
C
496 lines
14 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2006-2010 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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/*
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* Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
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*/
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#include <linux/slab.h>
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#include <linux/timer.h>
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#include <linux/delay.h>
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#include "efx.h"
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#include "mdio_10g.h"
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#include "phy.h"
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#include "nic.h"
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#define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \
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MDIO_DEVS_PMAPMD | \
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MDIO_DEVS_PHYXS)
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#define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \
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(1 << LOOPBACK_PMAPMD) | \
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(1 << LOOPBACK_PHYXS_WS))
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/****************************************************************************/
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/* Quake-specific MDIO registers */
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#define MDIO_QUAKE_LED0_REG (0xD006)
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/* QT2025C only */
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#define PCS_FW_HEARTBEAT_REG 0xd7ee
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#define PCS_FW_HEARTB_LBN 0
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#define PCS_FW_HEARTB_WIDTH 8
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#define PCS_FW_PRODUCT_CODE_1 0xd7f0
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#define PCS_FW_VERSION_1 0xd7f3
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#define PCS_FW_BUILD_1 0xd7f6
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#define PCS_UC8051_STATUS_REG 0xd7fd
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#define PCS_UC_STATUS_LBN 0
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#define PCS_UC_STATUS_WIDTH 8
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#define PCS_UC_STATUS_FW_SAVE 0x20
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#define PMA_PMD_MODE_REG 0xc301
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#define PMA_PMD_RXIN_SEL_LBN 6
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#define PMA_PMD_FTX_CTRL2_REG 0xc309
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#define PMA_PMD_FTX_STATIC_LBN 13
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#define PMA_PMD_VEND1_REG 0xc001
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#define PMA_PMD_VEND1_LBTXD_LBN 15
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#define PCS_VEND1_REG 0xc000
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#define PCS_VEND1_LBTXD_LBN 5
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void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
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{
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int addr = MDIO_QUAKE_LED0_REG + led;
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efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
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}
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struct qt202x_phy_data {
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enum efx_phy_mode phy_mode;
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bool bug17190_in_bad_state;
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unsigned long bug17190_timer;
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u32 firmware_ver;
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};
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#define QT2022C2_MAX_RESET_TIME 500
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#define QT2022C2_RESET_WAIT 10
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#define QT2025C_MAX_HEARTB_TIME (5 * HZ)
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#define QT2025C_HEARTB_WAIT 100
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#define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10)
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#define QT2025C_FWSTART_WAIT 100
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#define BUG17190_INTERVAL (2 * HZ)
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static int qt2025c_wait_heartbeat(struct efx_nic *efx)
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{
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unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME;
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int reg, old_counter = 0;
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/* Wait for firmware heartbeat to start */
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for (;;) {
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int counter;
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reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
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if (reg < 0)
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return reg;
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counter = ((reg >> PCS_FW_HEARTB_LBN) &
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((1 << PCS_FW_HEARTB_WIDTH) - 1));
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if (old_counter == 0)
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old_counter = counter;
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else if (counter != old_counter)
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break;
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if (time_after(jiffies, timeout)) {
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/* Some cables have EEPROMs that conflict with the
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* PHY's on-board EEPROM so it cannot load firmware */
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netif_err(efx, hw, efx->net_dev,
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"If an SFP+ direct attach cable is"
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" connected, please check that it complies"
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" with the SFP+ specification\n");
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return -ETIMEDOUT;
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}
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msleep(QT2025C_HEARTB_WAIT);
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}
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return 0;
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}
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static int qt2025c_wait_fw_status_good(struct efx_nic *efx)
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{
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unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME;
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int reg;
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/* Wait for firmware status to look good */
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for (;;) {
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reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
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if (reg < 0)
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return reg;
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if ((reg &
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((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
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PCS_UC_STATUS_FW_SAVE)
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break;
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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msleep(QT2025C_FWSTART_WAIT);
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}
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return 0;
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}
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static void qt2025c_restart_firmware(struct efx_nic *efx)
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{
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/* Restart microcontroller execution of firmware from RAM */
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efx_mdio_write(efx, 3, 0xe854, 0x00c0);
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efx_mdio_write(efx, 3, 0xe854, 0x0040);
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msleep(50);
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}
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static int qt2025c_wait_reset(struct efx_nic *efx)
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{
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int rc;
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rc = qt2025c_wait_heartbeat(efx);
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if (rc != 0)
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return rc;
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rc = qt2025c_wait_fw_status_good(efx);
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if (rc == -ETIMEDOUT) {
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/* Bug 17689: occasionally heartbeat starts but firmware status
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* code never progresses beyond 0x00. Try again, once, after
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* restarting execution of the firmware image. */
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netif_dbg(efx, hw, efx->net_dev,
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"bashing QT2025C microcontroller\n");
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qt2025c_restart_firmware(efx);
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rc = qt2025c_wait_heartbeat(efx);
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if (rc != 0)
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return rc;
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rc = qt2025c_wait_fw_status_good(efx);
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}
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return rc;
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}
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static void qt2025c_firmware_id(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data = efx->phy_data;
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u8 firmware_id[9];
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size_t i;
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for (i = 0; i < sizeof(firmware_id); i++)
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firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
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PCS_FW_PRODUCT_CODE_1 + i);
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netif_info(efx, probe, efx->net_dev,
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"QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
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(firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
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firmware_id[3] >> 4, firmware_id[3] & 0xf,
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firmware_id[4], firmware_id[5],
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firmware_id[6], firmware_id[7], firmware_id[8]);
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phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
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((firmware_id[3] & 0x0f) << 16) |
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(firmware_id[4] << 8) | firmware_id[5];
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}
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static void qt2025c_bug17190_workaround(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data = efx->phy_data;
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/* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
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* layers up, but PCS down (no block_lock). If we notice this state
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* persisting for a couple of seconds, we switch PMA/PMD loopback
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* briefly on and then off again, which is normally sufficient to
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* recover it.
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*/
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if (efx->link_state.up ||
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!efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) {
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phy_data->bug17190_in_bad_state = false;
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return;
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}
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if (!phy_data->bug17190_in_bad_state) {
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phy_data->bug17190_in_bad_state = true;
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phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
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return;
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}
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if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
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netif_dbg(efx, hw, efx->net_dev, "bashing QT2025C PMA/PMD\n");
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efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
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MDIO_PMA_CTRL1_LOOPBACK, true);
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msleep(100);
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efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
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MDIO_PMA_CTRL1_LOOPBACK, false);
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phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
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}
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}
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static int qt2025c_select_phy_mode(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data = efx->phy_data;
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struct falcon_board *board = falcon_board(efx);
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int reg, rc, i;
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uint16_t phy_op_mode;
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/* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
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* Self-Configure mode. Don't attempt any switching if we encounter
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* older firmware. */
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if (phy_data->firmware_ver < 0x02000100)
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return 0;
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/* In general we will get optimal behaviour in "SFP+ Self-Configure"
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* mode; however, that powers down most of the PHY when no module is
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* present, so we must use a different mode (any fixed mode will do)
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* to be sure that loopbacks will work. */
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phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
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/* Only change mode if really necessary */
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reg = efx_mdio_read(efx, 1, 0xc319);
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if ((reg & 0x0038) == phy_op_mode)
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return 0;
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netif_dbg(efx, hw, efx->net_dev, "Switching PHY to mode 0x%04x\n",
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phy_op_mode);
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/* This sequence replicates the register writes configured in the boot
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* EEPROM (including the differences between board revisions), except
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* that the operating mode is changed, and the PHY is prevented from
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* unnecessarily reloading the main firmware image again. */
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efx_mdio_write(efx, 1, 0xc300, 0x0000);
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/* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
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* STOPs onto the firmware/module I2C bus to reset it, varies across
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* board revisions, as the bus is connected to different GPIO/LED
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* outputs on the PHY.) */
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if (board->major == 0 && board->minor < 2) {
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efx_mdio_write(efx, 1, 0xc303, 0x4498);
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for (i = 0; i < 9; i++) {
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efx_mdio_write(efx, 1, 0xc303, 0x4488);
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efx_mdio_write(efx, 1, 0xc303, 0x4480);
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efx_mdio_write(efx, 1, 0xc303, 0x4490);
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efx_mdio_write(efx, 1, 0xc303, 0x4498);
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}
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} else {
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efx_mdio_write(efx, 1, 0xc303, 0x0920);
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efx_mdio_write(efx, 1, 0xd008, 0x0004);
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for (i = 0; i < 9; i++) {
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efx_mdio_write(efx, 1, 0xc303, 0x0900);
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efx_mdio_write(efx, 1, 0xd008, 0x0005);
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efx_mdio_write(efx, 1, 0xc303, 0x0920);
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efx_mdio_write(efx, 1, 0xd008, 0x0004);
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}
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efx_mdio_write(efx, 1, 0xc303, 0x4900);
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}
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efx_mdio_write(efx, 1, 0xc303, 0x4900);
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efx_mdio_write(efx, 1, 0xc302, 0x0004);
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efx_mdio_write(efx, 1, 0xc316, 0x0013);
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efx_mdio_write(efx, 1, 0xc318, 0x0054);
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efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
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efx_mdio_write(efx, 1, 0xc31a, 0x0098);
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efx_mdio_write(efx, 3, 0x0026, 0x0e00);
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efx_mdio_write(efx, 3, 0x0027, 0x0013);
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efx_mdio_write(efx, 3, 0x0028, 0xa528);
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efx_mdio_write(efx, 1, 0xd006, 0x000a);
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efx_mdio_write(efx, 1, 0xd007, 0x0009);
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efx_mdio_write(efx, 1, 0xd008, 0x0004);
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/* This additional write is not present in the boot EEPROM. It
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* prevents the PHY's internal boot ROM doing another pointless (and
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* slow) reload of the firmware image (the microcontroller's code
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* memory is not affected by the microcontroller reset). */
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efx_mdio_write(efx, 1, 0xc317, 0x00ff);
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/* PMA/PMD loopback sets RXIN to inverse polarity and the firmware
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* restart doesn't reset it. We need to do that ourselves. */
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efx_mdio_set_flag(efx, 1, PMA_PMD_MODE_REG,
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1 << PMA_PMD_RXIN_SEL_LBN, false);
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efx_mdio_write(efx, 1, 0xc300, 0x0002);
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msleep(20);
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/* Restart microcontroller execution of firmware from RAM */
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qt2025c_restart_firmware(efx);
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/* Wait for the microcontroller to be ready again */
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rc = qt2025c_wait_reset(efx);
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if (rc < 0) {
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netif_err(efx, hw, efx->net_dev,
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"PHY microcontroller reset during mode switch "
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"timed out\n");
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return rc;
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}
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return 0;
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}
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static int qt202x_reset_phy(struct efx_nic *efx)
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{
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int rc;
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if (efx->phy_type == PHY_TYPE_QT2025C) {
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/* Wait for the reset triggered by falcon_reset_hw()
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* to complete */
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rc = qt2025c_wait_reset(efx);
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if (rc < 0)
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goto fail;
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} else {
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/* Reset the PHYXS MMD. This is documented as doing
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* a complete soft reset. */
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rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
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QT2022C2_MAX_RESET_TIME /
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QT2022C2_RESET_WAIT,
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QT2022C2_RESET_WAIT);
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if (rc < 0)
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goto fail;
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}
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/* Wait 250ms for the PHY to complete bootup */
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msleep(250);
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falcon_board(efx)->type->init_phy(efx);
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return 0;
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fail:
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netif_err(efx, hw, efx->net_dev, "PHY reset timed out\n");
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return rc;
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}
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static int qt202x_phy_probe(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data;
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phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
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if (!phy_data)
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return -ENOMEM;
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efx->phy_data = phy_data;
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phy_data->phy_mode = efx->phy_mode;
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phy_data->bug17190_in_bad_state = false;
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phy_data->bug17190_timer = 0;
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efx->mdio.mmds = QT202X_REQUIRED_DEVS;
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efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
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efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
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return 0;
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}
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static int qt202x_phy_init(struct efx_nic *efx)
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{
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u32 devid;
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int rc;
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rc = qt202x_reset_phy(efx);
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if (rc) {
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netif_err(efx, probe, efx->net_dev, "PHY init failed\n");
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return rc;
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}
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devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
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netif_info(efx, probe, efx->net_dev,
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"PHY ID reg %x (OUI %06x model %02x revision %x)\n",
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devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
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efx_mdio_id_rev(devid));
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if (efx->phy_type == PHY_TYPE_QT2025C)
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qt2025c_firmware_id(efx);
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return 0;
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}
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static int qt202x_link_ok(struct efx_nic *efx)
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{
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return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
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}
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static bool qt202x_phy_poll(struct efx_nic *efx)
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{
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bool was_up = efx->link_state.up;
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efx->link_state.up = qt202x_link_ok(efx);
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efx->link_state.speed = 10000;
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efx->link_state.fd = true;
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efx->link_state.fc = efx->wanted_fc;
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if (efx->phy_type == PHY_TYPE_QT2025C)
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qt2025c_bug17190_workaround(efx);
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return efx->link_state.up != was_up;
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}
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static int qt202x_phy_reconfigure(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data = efx->phy_data;
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if (efx->phy_type == PHY_TYPE_QT2025C) {
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int rc = qt2025c_select_phy_mode(efx);
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if (rc)
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return rc;
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/* There are several different register bits which can
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* disable TX (and save power) on direct-attach cables
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* or optical transceivers, varying somewhat between
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* firmware versions. Only 'static mode' appears to
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* cover everything. */
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mdio_set_flag(
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&efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
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PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
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efx->phy_mode & PHY_MODE_TX_DISABLED ||
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efx->phy_mode & PHY_MODE_LOW_POWER ||
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efx->loopback_mode == LOOPBACK_PCS ||
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efx->loopback_mode == LOOPBACK_PMAPMD);
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} else {
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/* Reset the PHY when moving from tx off to tx on */
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if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
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(phy_data->phy_mode & PHY_MODE_TX_DISABLED))
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qt202x_reset_phy(efx);
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efx_mdio_transmit_disable(efx);
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}
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efx_mdio_phy_reconfigure(efx);
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phy_data->phy_mode = efx->phy_mode;
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|
return 0;
|
|
}
|
|
|
|
static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
|
|
{
|
|
mdio45_ethtool_gset(&efx->mdio, ecmd);
|
|
}
|
|
|
|
static void qt202x_phy_remove(struct efx_nic *efx)
|
|
{
|
|
/* Free the context block */
|
|
kfree(efx->phy_data);
|
|
efx->phy_data = NULL;
|
|
}
|
|
|
|
static int qt202x_phy_get_module_info(struct efx_nic *efx,
|
|
struct ethtool_modinfo *modinfo)
|
|
{
|
|
modinfo->type = ETH_MODULE_SFF_8079;
|
|
modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
|
|
return 0;
|
|
}
|
|
|
|
static int qt202x_phy_get_module_eeprom(struct efx_nic *efx,
|
|
struct ethtool_eeprom *ee, u8 *data)
|
|
{
|
|
int mmd, reg_base, rc, i;
|
|
|
|
if (efx->phy_type == PHY_TYPE_QT2025C) {
|
|
mmd = MDIO_MMD_PCS;
|
|
reg_base = 0xd000;
|
|
} else {
|
|
mmd = MDIO_MMD_PMAPMD;
|
|
reg_base = 0x8007;
|
|
}
|
|
|
|
for (i = 0; i < ee->len; i++) {
|
|
rc = efx_mdio_read(efx, mmd, reg_base + ee->offset + i);
|
|
if (rc < 0)
|
|
return rc;
|
|
data[i] = rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct efx_phy_operations falcon_qt202x_phy_ops = {
|
|
.probe = qt202x_phy_probe,
|
|
.init = qt202x_phy_init,
|
|
.reconfigure = qt202x_phy_reconfigure,
|
|
.poll = qt202x_phy_poll,
|
|
.fini = efx_port_dummy_op_void,
|
|
.remove = qt202x_phy_remove,
|
|
.get_settings = qt202x_phy_get_settings,
|
|
.set_settings = efx_mdio_set_settings,
|
|
.test_alive = efx_mdio_test_alive,
|
|
.get_module_eeprom = qt202x_phy_get_module_eeprom,
|
|
.get_module_info = qt202x_phy_get_module_info,
|
|
};
|