64 lines
1.5 KiB
C
64 lines
1.5 KiB
C
/*
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* include/asm-arm/arch-ixp23xx/memory.h
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*
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* Copyright (c) 2003-2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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#include <asm/hardware.h>
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/*
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* Physical DRAM offset.
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*/
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#define PHYS_OFFSET (0x00000000)
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/*
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* Virtual view <-> DMA view memory address translations
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* virt_to_bus: Used to translate the virtual address to an
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* address suitable to be passed to set_dma_addr
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* bus_to_virt: Used to convert an address for DMA operations
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* to an address that the kernel can use.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/mach-types.h>
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#define __virt_to_bus(v) \
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({ unsigned int ret; \
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ret = ((__virt_to_phys(v) - 0x00000000) + \
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(*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)); \
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ret; })
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#define __bus_to_virt(b) \
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({ unsigned int data; \
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data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \
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__phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
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/*
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* Coherency support. Only supported on A2 CPUs or on A1
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* systems that have the cache coherency workaround.
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*/
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static inline int __ixp23xx_arch_is_coherent(void)
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{
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extern unsigned int processor_id;
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if (((processor_id & 15) >= 4) || machine_is_roadrunner())
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return 1;
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return 0;
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}
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#define arch_is_coherent() __ixp23xx_arch_is_coherent()
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#endif
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#endif
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