1482 lines
43 KiB
C
1482 lines
43 KiB
C
/*
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* exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
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*
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* Copyright (C) 2014 Samsung Electronics
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* Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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* Lukasz Majewski <l.majewski@samsung.com>
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*
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* Copyright (C) 2011 Samsung Electronics
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* Donggeun Kim <dg77.kim@samsung.com>
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* Amit Daniel Kachhap <amit.kachhap@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include "exynos_tmu.h"
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#include "../thermal_core.h"
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/* Exynos generic registers */
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#define EXYNOS_TMU_REG_TRIMINFO 0x0
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#define EXYNOS_TMU_REG_CONTROL 0x20
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#define EXYNOS_TMU_REG_STATUS 0x28
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#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
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#define EXYNOS_TMU_REG_INTEN 0x70
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#define EXYNOS_TMU_REG_INTSTAT 0x74
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#define EXYNOS_TMU_REG_INTCLEAR 0x78
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#define EXYNOS_TMU_TEMP_MASK 0xff
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#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
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#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
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#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
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#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
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#define EXYNOS_TMU_CORE_EN_SHIFT 0
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/* Exynos3250 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON1 0x10
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/* Exynos4210 specific registers */
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#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
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#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
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/* Exynos5250, Exynos4412, Exynos3250 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON2 0x14
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#define EXYNOS_THD_TEMP_RISE 0x50
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#define EXYNOS_THD_TEMP_FALL 0x54
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#define EXYNOS_EMUL_CON 0x80
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#define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
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#define EXYNOS_TRIMINFO_25_SHIFT 0
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#define EXYNOS_TRIMINFO_85_SHIFT 8
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#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
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#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
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#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
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#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
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#define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
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#define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
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#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
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#define EXYNOS_EMUL_TIME 0x57F0
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#define EXYNOS_EMUL_TIME_MASK 0xffff
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#define EXYNOS_EMUL_TIME_SHIFT 16
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#define EXYNOS_EMUL_DATA_SHIFT 8
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#define EXYNOS_EMUL_DATA_MASK 0xFF
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#define EXYNOS_EMUL_ENABLE 0x1
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/* Exynos5260 specific */
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#define EXYNOS5260_TMU_REG_INTEN 0xC0
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#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
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#define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
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#define EXYNOS5260_EMUL_CON 0x100
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/* Exynos4412 specific */
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#define EXYNOS4412_MUX_ADDR_VALUE 6
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#define EXYNOS4412_MUX_ADDR_SHIFT 20
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/* Exynos5433 specific registers */
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#define EXYNOS5433_TMU_REG_CONTROL1 0x024
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#define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c
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#define EXYNOS5433_TMU_COUNTER_VALUE0 0x030
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#define EXYNOS5433_TMU_COUNTER_VALUE1 0x034
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#define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044
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#define EXYNOS5433_THD_TEMP_RISE3_0 0x050
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#define EXYNOS5433_THD_TEMP_RISE7_4 0x054
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#define EXYNOS5433_THD_TEMP_FALL3_0 0x060
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#define EXYNOS5433_THD_TEMP_FALL7_4 0x064
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#define EXYNOS5433_TMU_REG_INTEN 0x0c0
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#define EXYNOS5433_TMU_REG_INTPEND 0x0c8
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#define EXYNOS5433_TMU_EMUL_CON 0x110
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#define EXYNOS5433_TMU_PD_DET_EN 0x130
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#define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16
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#define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23
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#define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \
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(0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
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#define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23)
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#define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0
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#define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1
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#define EXYNOS5433_PD_DET_EN 1
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/*exynos5440 specific registers*/
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#define EXYNOS5440_TMU_S0_7_TRIM 0x000
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#define EXYNOS5440_TMU_S0_7_CTRL 0x020
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#define EXYNOS5440_TMU_S0_7_DEBUG 0x040
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#define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
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#define EXYNOS5440_TMU_S0_7_TH0 0x110
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#define EXYNOS5440_TMU_S0_7_TH1 0x130
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#define EXYNOS5440_TMU_S0_7_TH2 0x150
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#define EXYNOS5440_TMU_S0_7_IRQEN 0x210
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#define EXYNOS5440_TMU_S0_7_IRQ 0x230
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/* exynos5440 common registers */
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#define EXYNOS5440_TMU_IRQ_STATUS 0x000
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#define EXYNOS5440_TMU_PMIN 0x004
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#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
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#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
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#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
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#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
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#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
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#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
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/* Exynos7 specific registers */
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#define EXYNOS7_THD_TEMP_RISE7_6 0x50
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#define EXYNOS7_THD_TEMP_FALL7_6 0x60
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#define EXYNOS7_TMU_REG_INTEN 0x110
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#define EXYNOS7_TMU_REG_INTPEND 0x118
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#define EXYNOS7_TMU_REG_EMUL_CON 0x160
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#define EXYNOS7_TMU_TEMP_MASK 0x1ff
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#define EXYNOS7_PD_DET_EN_SHIFT 23
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#define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1
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#define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2
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#define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3
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#define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4
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#define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5
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#define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6
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#define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7
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#define EXYNOS7_EMUL_DATA_SHIFT 7
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#define EXYNOS7_EMUL_DATA_MASK 0x1ff
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#define MCELSIUS 1000
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/**
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* struct exynos_tmu_data : A structure to hold the private data of the TMU
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driver
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* @id: identifier of the one instance of the TMU controller.
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* @pdata: pointer to the tmu platform/configuration data
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* @base: base address of the single instance of the TMU controller.
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* @base_second: base address of the common registers of the TMU controller.
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* @irq: irq number of the TMU controller.
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* @soc: id of the SOC type.
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* @irq_work: pointer to the irq work structure.
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* @lock: lock to implement synchronization.
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* @clk: pointer to the clock structure.
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* @clk_sec: pointer to the clock structure for accessing the base_second.
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* @sclk: pointer to the clock structure for accessing the tmu special clk.
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* @temp_error1: fused value of the first point trim.
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* @temp_error2: fused value of the second point trim.
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* @regulator: pointer to the TMU regulator structure.
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* @reg_conf: pointer to structure to register with core thermal.
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* @ntrip: number of supported trip points.
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* @tmu_initialize: SoC specific TMU initialization method
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* @tmu_control: SoC specific TMU control method
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* @tmu_read: SoC specific TMU temperature read method
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* @tmu_set_emulation: SoC specific TMU emulation setting method
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* @tmu_clear_irqs: SoC specific TMU interrupts clearing method
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*/
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struct exynos_tmu_data {
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int id;
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struct exynos_tmu_platform_data *pdata;
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void __iomem *base;
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void __iomem *base_second;
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int irq;
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enum soc_type soc;
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struct work_struct irq_work;
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struct mutex lock;
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struct clk *clk, *clk_sec, *sclk;
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u16 temp_error1, temp_error2;
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struct regulator *regulator;
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struct thermal_zone_device *tzd;
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unsigned int ntrip;
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int (*tmu_initialize)(struct platform_device *pdev);
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void (*tmu_control)(struct platform_device *pdev, bool on);
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int (*tmu_read)(struct exynos_tmu_data *data);
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void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
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void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
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};
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static void exynos_report_trigger(struct exynos_tmu_data *p)
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{
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char data[10], *envp[] = { data, NULL };
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struct thermal_zone_device *tz = p->tzd;
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int temp;
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unsigned int i;
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if (!tz) {
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pr_err("No thermal zone device defined\n");
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return;
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}
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thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
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mutex_lock(&tz->lock);
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/* Find the level for which trip happened */
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for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
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tz->ops->get_trip_temp(tz, i, &temp);
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if (tz->last_temperature < temp)
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break;
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}
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snprintf(data, sizeof(data), "%u", i);
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kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
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mutex_unlock(&tz->lock);
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}
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/*
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* TMU treats temperature as a mapped temperature code.
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* The temperature is converted differently depending on the calibration type.
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*/
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static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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int temp_code;
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switch (pdata->cal_type) {
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case TYPE_TWO_POINT_TRIMMING:
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temp_code = (temp - pdata->first_point_trim) *
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(data->temp_error2 - data->temp_error1) /
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(pdata->second_point_trim - pdata->first_point_trim) +
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data->temp_error1;
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break;
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case TYPE_ONE_POINT_TRIMMING:
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temp_code = temp + data->temp_error1 - pdata->first_point_trim;
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break;
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default:
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temp_code = temp + pdata->default_temp_offset;
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break;
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}
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return temp_code;
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}
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/*
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* Calculate a temperature value from a temperature code.
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* The unit of the temperature is degree Celsius.
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*/
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static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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int temp;
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switch (pdata->cal_type) {
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case TYPE_TWO_POINT_TRIMMING:
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temp = (temp_code - data->temp_error1) *
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(pdata->second_point_trim - pdata->first_point_trim) /
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(data->temp_error2 - data->temp_error1) +
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pdata->first_point_trim;
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break;
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case TYPE_ONE_POINT_TRIMMING:
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temp = temp_code - data->temp_error1 + pdata->first_point_trim;
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break;
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default:
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temp = temp_code - pdata->default_temp_offset;
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break;
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}
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return temp;
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}
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static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
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data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK);
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if (!data->temp_error1 ||
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(pdata->min_efuse_value > data->temp_error1) ||
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(data->temp_error1 > pdata->max_efuse_value))
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data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
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if (!data->temp_error2)
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data->temp_error2 =
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(pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK;
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}
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static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
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{
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struct thermal_zone_device *tz = data->tzd;
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(tz);
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unsigned long temp;
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int i;
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if (!trips) {
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pr_err("%s: Cannot get trip points from of-thermal.c!\n",
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__func__);
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return 0;
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}
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for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
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if (trips[i].type == THERMAL_TRIP_CRITICAL)
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continue;
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temp = trips[i].temperature / MCELSIUS;
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if (falling)
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temp -= (trips[i].hysteresis / MCELSIUS);
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else
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threshold &= ~(0xff << 8 * i);
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threshold |= temp_to_code(data, temp) << 8 * i;
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}
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return threshold;
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}
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static int exynos_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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int ret;
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if (of_thermal_get_ntrips(data->tzd) > data->ntrip) {
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dev_info(&pdev->dev,
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"More trip points than supported by this TMU.\n");
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dev_info(&pdev->dev,
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"%d trip points should be configured in polling mode.\n",
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(of_thermal_get_ntrips(data->tzd) - data->ntrip));
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}
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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ret = data->tmu_initialize(pdev);
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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if (!IS_ERR(data->clk_sec))
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clk_disable(data->clk_sec);
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return ret;
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}
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static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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if (data->soc == SOC_ARCH_EXYNOS4412 ||
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data->soc == SOC_ARCH_EXYNOS3250)
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con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
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con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
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con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
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con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
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con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
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if (pdata->noise_cancel_mode) {
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con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
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con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
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}
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return con;
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}
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static void exynos_tmu_control(struct platform_device *pdev, bool on)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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data->tmu_control(pdev, on);
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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}
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static int exynos4210_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tz = data->tzd;
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(tz);
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int ret = 0, threshold_code, i;
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unsigned long reference, temp;
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unsigned int status;
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if (!trips) {
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pr_err("%s: Cannot get trip points from of-thermal.c!\n",
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__func__);
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ret = -ENODEV;
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goto out;
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}
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status = readb(data->base + EXYNOS_TMU_REG_STATUS);
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if (!status) {
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ret = -EBUSY;
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goto out;
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}
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sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
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/* Write temperature code for threshold */
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reference = trips[0].temperature / MCELSIUS;
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threshold_code = temp_to_code(data, reference);
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if (threshold_code < 0) {
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ret = threshold_code;
|
|
goto out;
|
|
}
|
|
writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
|
|
|
|
for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
|
|
temp = trips[i].temperature / MCELSIUS;
|
|
writeb(temp - reference, data->base +
|
|
EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
|
|
}
|
|
|
|
data->tmu_clear_irqs(data);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int exynos4412_tmu_initialize(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
const struct thermal_trip * const trips =
|
|
of_thermal_get_trip_points(data->tzd);
|
|
unsigned int status, trim_info, con, ctrl, rising_threshold;
|
|
int ret = 0, threshold_code, i;
|
|
unsigned long crit_temp = 0;
|
|
|
|
status = readb(data->base + EXYNOS_TMU_REG_STATUS);
|
|
if (!status) {
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS3250 ||
|
|
data->soc == SOC_ARCH_EXYNOS4412 ||
|
|
data->soc == SOC_ARCH_EXYNOS5250) {
|
|
if (data->soc == SOC_ARCH_EXYNOS3250) {
|
|
ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
|
|
ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
|
|
writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
|
|
}
|
|
ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
|
|
ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
|
|
writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
|
|
}
|
|
|
|
/* On exynos5420 the triminfo register is in the shared space */
|
|
if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
|
|
trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
|
|
else
|
|
trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
|
|
sanitize_temp_error(data, trim_info);
|
|
|
|
/* Write temperature code for rising and falling threshold */
|
|
rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
|
|
rising_threshold = get_th_reg(data, rising_threshold, false);
|
|
writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
|
|
writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
|
|
|
|
data->tmu_clear_irqs(data);
|
|
|
|
/* if last threshold limit is also present */
|
|
for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
|
|
if (trips[i].type == THERMAL_TRIP_CRITICAL) {
|
|
crit_temp = trips[i].temperature;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i == of_thermal_get_ntrips(data->tzd)) {
|
|
pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n",
|
|
__func__);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
|
|
/* 1-4 level to be assigned in th0 reg */
|
|
rising_threshold &= ~(0xff << 8 * i);
|
|
rising_threshold |= threshold_code << 8 * i;
|
|
writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
|
|
con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
|
|
con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
|
|
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int exynos5433_tmu_initialize(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int status, trim_info;
|
|
unsigned int rising_threshold = 0, falling_threshold = 0;
|
|
int temp, temp_hist;
|
|
int ret = 0, threshold_code, i, sensor_id, cal_type;
|
|
|
|
status = readb(data->base + EXYNOS_TMU_REG_STATUS);
|
|
if (!status) {
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
sanitize_temp_error(data, trim_info);
|
|
|
|
/* Read the temperature sensor id */
|
|
sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK)
|
|
>> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT;
|
|
dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id);
|
|
|
|
/* Read the calibration mode */
|
|
writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK)
|
|
>> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT;
|
|
|
|
switch (cal_type) {
|
|
case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING:
|
|
pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
|
|
break;
|
|
case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING:
|
|
pdata->cal_type = TYPE_TWO_POINT_TRIMMING;
|
|
break;
|
|
default:
|
|
pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
|
|
break;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Calibration type is %d-point calibration\n",
|
|
cal_type ? 2 : 1);
|
|
|
|
/* Write temperature code for rising and falling threshold */
|
|
for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
|
|
int rising_reg_offset, falling_reg_offset;
|
|
int j = 0;
|
|
|
|
switch (i) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
rising_reg_offset = EXYNOS5433_THD_TEMP_RISE3_0;
|
|
falling_reg_offset = EXYNOS5433_THD_TEMP_FALL3_0;
|
|
j = i;
|
|
break;
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
rising_reg_offset = EXYNOS5433_THD_TEMP_RISE7_4;
|
|
falling_reg_offset = EXYNOS5433_THD_TEMP_FALL7_4;
|
|
j = i - 4;
|
|
break;
|
|
default:
|
|
continue;
|
|
}
|
|
|
|
/* Write temperature code for rising threshold */
|
|
tz->ops->get_trip_temp(tz, i, &temp);
|
|
temp /= MCELSIUS;
|
|
threshold_code = temp_to_code(data, temp);
|
|
|
|
rising_threshold = readl(data->base + rising_reg_offset);
|
|
rising_threshold |= (threshold_code << j * 8);
|
|
writel(rising_threshold, data->base + rising_reg_offset);
|
|
|
|
/* Write temperature code for falling threshold */
|
|
tz->ops->get_trip_hyst(tz, i, &temp_hist);
|
|
temp_hist = temp - (temp_hist / MCELSIUS);
|
|
threshold_code = temp_to_code(data, temp_hist);
|
|
|
|
falling_threshold = readl(data->base + falling_reg_offset);
|
|
falling_threshold &= ~(0xff << j * 8);
|
|
falling_threshold |= (threshold_code << j * 8);
|
|
writel(falling_threshold, data->base + falling_reg_offset);
|
|
}
|
|
|
|
data->tmu_clear_irqs(data);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int exynos5440_tmu_initialize(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
unsigned int trim_info = 0, con, rising_threshold;
|
|
int threshold_code;
|
|
int crit_temp = 0;
|
|
|
|
/*
|
|
* For exynos5440 soc triminfo value is swapped between TMU0 and
|
|
* TMU2, so the below logic is needed.
|
|
*/
|
|
switch (data->id) {
|
|
case 0:
|
|
trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
|
|
EXYNOS5440_TMU_S0_7_TRIM);
|
|
break;
|
|
case 1:
|
|
trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
|
|
break;
|
|
case 2:
|
|
trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
|
|
EXYNOS5440_TMU_S0_7_TRIM);
|
|
}
|
|
sanitize_temp_error(data, trim_info);
|
|
|
|
/* Write temperature code for rising and falling threshold */
|
|
rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
|
|
rising_threshold = get_th_reg(data, rising_threshold, false);
|
|
writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
|
|
writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
|
|
|
|
data->tmu_clear_irqs(data);
|
|
|
|
/* if last threshold limit is also present */
|
|
if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
|
|
threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
|
|
/* 5th level to be assigned in th2 reg */
|
|
rising_threshold =
|
|
threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
|
|
writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
|
|
con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
|
|
con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
|
|
writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
|
|
}
|
|
/* Clear the PMIN in the common TMU register */
|
|
if (!data->id)
|
|
writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos7_tmu_initialize(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
|
unsigned int status, trim_info;
|
|
unsigned int rising_threshold = 0, falling_threshold = 0;
|
|
int ret = 0, threshold_code, i;
|
|
int temp, temp_hist;
|
|
unsigned int reg_off, bit_off;
|
|
|
|
status = readb(data->base + EXYNOS_TMU_REG_STATUS);
|
|
if (!status) {
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
|
|
data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
|
|
if (!data->temp_error1 ||
|
|
(pdata->min_efuse_value > data->temp_error1) ||
|
|
(data->temp_error1 > pdata->max_efuse_value))
|
|
data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
|
|
|
|
/* Write temperature code for rising and falling threshold */
|
|
for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
|
|
/*
|
|
* On exynos7 there are 4 rising and 4 falling threshold
|
|
* registers (0x50-0x5c and 0x60-0x6c respectively). Each
|
|
* register holds the value of two threshold levels (at bit
|
|
* offsets 0 and 16). Based on the fact that there are atmost
|
|
* eight possible trigger levels, calculate the register and
|
|
* bit offsets where the threshold levels are to be written.
|
|
*
|
|
* e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50)
|
|
* [24:16] - Threshold level 7
|
|
* [8:0] - Threshold level 6
|
|
* e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54)
|
|
* [24:16] - Threshold level 5
|
|
* [8:0] - Threshold level 4
|
|
*
|
|
* and similarly for falling thresholds.
|
|
*
|
|
* Based on the above, calculate the register and bit offsets
|
|
* for rising/falling threshold levels and populate them.
|
|
*/
|
|
reg_off = ((7 - i) / 2) * 4;
|
|
bit_off = ((8 - i) % 2);
|
|
|
|
tz->ops->get_trip_temp(tz, i, &temp);
|
|
temp /= MCELSIUS;
|
|
|
|
tz->ops->get_trip_hyst(tz, i, &temp_hist);
|
|
temp_hist = temp - (temp_hist / MCELSIUS);
|
|
|
|
/* Set 9-bit temperature code for rising threshold levels */
|
|
threshold_code = temp_to_code(data, temp);
|
|
rising_threshold = readl(data->base +
|
|
EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
|
|
rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
|
|
rising_threshold |= threshold_code << (16 * bit_off);
|
|
writel(rising_threshold,
|
|
data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
|
|
|
|
/* Set 9-bit temperature code for falling threshold levels */
|
|
threshold_code = temp_to_code(data, temp_hist);
|
|
falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
|
|
falling_threshold |= threshold_code << (16 * bit_off);
|
|
writel(falling_threshold,
|
|
data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
|
|
}
|
|
|
|
data->tmu_clear_irqs(data);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int con, interrupt_en;
|
|
|
|
con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
|
|
|
|
if (on) {
|
|
con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
interrupt_en =
|
|
(of_thermal_is_trip_valid(tz, 3)
|
|
<< EXYNOS_TMU_INTEN_RISE3_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 2)
|
|
<< EXYNOS_TMU_INTEN_RISE2_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 1)
|
|
<< EXYNOS_TMU_INTEN_RISE1_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 0)
|
|
<< EXYNOS_TMU_INTEN_RISE0_SHIFT);
|
|
|
|
if (data->soc != SOC_ARCH_EXYNOS4210)
|
|
interrupt_en |=
|
|
interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
|
|
} else {
|
|
con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
interrupt_en = 0; /* Disable all interrupts */
|
|
}
|
|
writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
|
|
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
|
|
}
|
|
|
|
static void exynos5433_tmu_control(struct platform_device *pdev, bool on)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int con, interrupt_en, pd_det_en;
|
|
|
|
con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
|
|
|
|
if (on) {
|
|
con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
interrupt_en =
|
|
(of_thermal_is_trip_valid(tz, 7)
|
|
<< EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 6)
|
|
<< EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 5)
|
|
<< EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 4)
|
|
<< EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 3)
|
|
<< EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 2)
|
|
<< EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 1)
|
|
<< EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 0)
|
|
<< EXYNOS7_TMU_INTEN_RISE0_SHIFT);
|
|
|
|
interrupt_en |=
|
|
interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
|
|
} else {
|
|
con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
interrupt_en = 0; /* Disable all interrupts */
|
|
}
|
|
|
|
pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0;
|
|
|
|
writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
|
|
writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN);
|
|
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
|
|
}
|
|
|
|
static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int con, interrupt_en;
|
|
|
|
con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
|
|
|
|
if (on) {
|
|
con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
interrupt_en =
|
|
(of_thermal_is_trip_valid(tz, 3)
|
|
<< EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 2)
|
|
<< EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 1)
|
|
<< EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 0)
|
|
<< EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
|
|
interrupt_en |=
|
|
interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
|
|
} else {
|
|
con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
interrupt_en = 0; /* Disable all interrupts */
|
|
}
|
|
writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
|
|
writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
|
|
}
|
|
|
|
static void exynos7_tmu_control(struct platform_device *pdev, bool on)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int con, interrupt_en;
|
|
|
|
con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
|
|
|
|
if (on) {
|
|
con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
con |= (1 << EXYNOS7_PD_DET_EN_SHIFT);
|
|
interrupt_en =
|
|
(of_thermal_is_trip_valid(tz, 7)
|
|
<< EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 6)
|
|
<< EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 5)
|
|
<< EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 4)
|
|
<< EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 3)
|
|
<< EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 2)
|
|
<< EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 1)
|
|
<< EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
|
|
(of_thermal_is_trip_valid(tz, 0)
|
|
<< EXYNOS7_TMU_INTEN_RISE0_SHIFT);
|
|
|
|
interrupt_en |=
|
|
interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
|
|
} else {
|
|
con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT);
|
|
interrupt_en = 0; /* Disable all interrupts */
|
|
}
|
|
|
|
writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
|
|
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
|
|
}
|
|
|
|
static int exynos_get_temp(void *p, int *temp)
|
|
{
|
|
struct exynos_tmu_data *data = p;
|
|
|
|
if (!data || !data->tmu_read)
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&data->lock);
|
|
clk_enable(data->clk);
|
|
|
|
*temp = code_to_temp(data, data->tmu_read(data)) * MCELSIUS;
|
|
|
|
clk_disable(data->clk);
|
|
mutex_unlock(&data->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_THERMAL_EMULATION
|
|
static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
|
|
int temp)
|
|
{
|
|
if (temp) {
|
|
temp /= MCELSIUS;
|
|
|
|
if (data->soc != SOC_ARCH_EXYNOS5440) {
|
|
val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
|
|
val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
|
|
}
|
|
if (data->soc == SOC_ARCH_EXYNOS7) {
|
|
val &= ~(EXYNOS7_EMUL_DATA_MASK <<
|
|
EXYNOS7_EMUL_DATA_SHIFT);
|
|
val |= (temp_to_code(data, temp) <<
|
|
EXYNOS7_EMUL_DATA_SHIFT) |
|
|
EXYNOS_EMUL_ENABLE;
|
|
} else {
|
|
val &= ~(EXYNOS_EMUL_DATA_MASK <<
|
|
EXYNOS_EMUL_DATA_SHIFT);
|
|
val |= (temp_to_code(data, temp) <<
|
|
EXYNOS_EMUL_DATA_SHIFT) |
|
|
EXYNOS_EMUL_ENABLE;
|
|
}
|
|
} else {
|
|
val &= ~EXYNOS_EMUL_ENABLE;
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
|
|
int temp)
|
|
{
|
|
unsigned int val;
|
|
u32 emul_con;
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS5260)
|
|
emul_con = EXYNOS5260_EMUL_CON;
|
|
else if (data->soc == SOC_ARCH_EXYNOS5433)
|
|
emul_con = EXYNOS5433_TMU_EMUL_CON;
|
|
else if (data->soc == SOC_ARCH_EXYNOS7)
|
|
emul_con = EXYNOS7_TMU_REG_EMUL_CON;
|
|
else
|
|
emul_con = EXYNOS_EMUL_CON;
|
|
|
|
val = readl(data->base + emul_con);
|
|
val = get_emul_con_reg(data, val, temp);
|
|
writel(val, data->base + emul_con);
|
|
}
|
|
|
|
static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
|
|
int temp)
|
|
{
|
|
unsigned int val;
|
|
|
|
val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
|
|
val = get_emul_con_reg(data, val, temp);
|
|
writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
|
|
}
|
|
|
|
static int exynos_tmu_set_emulation(void *drv_data, int temp)
|
|
{
|
|
struct exynos_tmu_data *data = drv_data;
|
|
int ret = -EINVAL;
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS4210)
|
|
goto out;
|
|
|
|
if (temp && temp < MCELSIUS)
|
|
goto out;
|
|
|
|
mutex_lock(&data->lock);
|
|
clk_enable(data->clk);
|
|
data->tmu_set_emulation(data, temp);
|
|
clk_disable(data->clk);
|
|
mutex_unlock(&data->lock);
|
|
return 0;
|
|
out:
|
|
return ret;
|
|
}
|
|
#else
|
|
#define exynos4412_tmu_set_emulation NULL
|
|
#define exynos5440_tmu_set_emulation NULL
|
|
static int exynos_tmu_set_emulation(void *drv_data, int temp)
|
|
{ return -EINVAL; }
|
|
#endif /* CONFIG_THERMAL_EMULATION */
|
|
|
|
static int exynos4210_tmu_read(struct exynos_tmu_data *data)
|
|
{
|
|
int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
|
|
|
|
/* "temp_code" should range between 75 and 175 */
|
|
return (ret < 75 || ret > 175) ? -ENODATA : ret;
|
|
}
|
|
|
|
static int exynos4412_tmu_read(struct exynos_tmu_data *data)
|
|
{
|
|
return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
|
|
}
|
|
|
|
static int exynos5440_tmu_read(struct exynos_tmu_data *data)
|
|
{
|
|
return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
|
|
}
|
|
|
|
static int exynos7_tmu_read(struct exynos_tmu_data *data)
|
|
{
|
|
return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
|
|
EXYNOS7_TMU_TEMP_MASK;
|
|
}
|
|
|
|
static void exynos_tmu_work(struct work_struct *work)
|
|
{
|
|
struct exynos_tmu_data *data = container_of(work,
|
|
struct exynos_tmu_data, irq_work);
|
|
unsigned int val_type;
|
|
|
|
if (!IS_ERR(data->clk_sec))
|
|
clk_enable(data->clk_sec);
|
|
/* Find which sensor generated this interrupt */
|
|
if (data->soc == SOC_ARCH_EXYNOS5440) {
|
|
val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
|
|
if (!((val_type >> data->id) & 0x1))
|
|
goto out;
|
|
}
|
|
if (!IS_ERR(data->clk_sec))
|
|
clk_disable(data->clk_sec);
|
|
|
|
exynos_report_trigger(data);
|
|
mutex_lock(&data->lock);
|
|
clk_enable(data->clk);
|
|
|
|
/* TODO: take action based on particular interrupt */
|
|
data->tmu_clear_irqs(data);
|
|
|
|
clk_disable(data->clk);
|
|
mutex_unlock(&data->lock);
|
|
out:
|
|
enable_irq(data->irq);
|
|
}
|
|
|
|
static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
|
|
{
|
|
unsigned int val_irq;
|
|
u32 tmu_intstat, tmu_intclear;
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS5260) {
|
|
tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
|
|
tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
|
|
} else if (data->soc == SOC_ARCH_EXYNOS7) {
|
|
tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
|
|
tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
|
|
} else if (data->soc == SOC_ARCH_EXYNOS5433) {
|
|
tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
|
|
tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
|
|
} else {
|
|
tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
|
|
tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
|
|
}
|
|
|
|
val_irq = readl(data->base + tmu_intstat);
|
|
/*
|
|
* Clear the interrupts. Please note that the documentation for
|
|
* Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
|
|
* states that INTCLEAR register has a different placing of bits
|
|
* responsible for FALL IRQs than INTSTAT register. Exynos5420
|
|
* and Exynos5440 documentation is correct (Exynos4210 doesn't
|
|
* support FALL IRQs at all).
|
|
*/
|
|
writel(val_irq, data->base + tmu_intclear);
|
|
}
|
|
|
|
static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
|
|
{
|
|
unsigned int val_irq;
|
|
|
|
val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
|
|
/* clear the interrupts */
|
|
writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
|
|
}
|
|
|
|
static irqreturn_t exynos_tmu_irq(int irq, void *id)
|
|
{
|
|
struct exynos_tmu_data *data = id;
|
|
|
|
disable_irq_nosync(irq);
|
|
schedule_work(&data->irq_work);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct of_device_id exynos_tmu_match[] = {
|
|
{ .compatible = "samsung,exynos3250-tmu", },
|
|
{ .compatible = "samsung,exynos4210-tmu", },
|
|
{ .compatible = "samsung,exynos4412-tmu", },
|
|
{ .compatible = "samsung,exynos5250-tmu", },
|
|
{ .compatible = "samsung,exynos5260-tmu", },
|
|
{ .compatible = "samsung,exynos5420-tmu", },
|
|
{ .compatible = "samsung,exynos5420-tmu-ext-triminfo", },
|
|
{ .compatible = "samsung,exynos5433-tmu", },
|
|
{ .compatible = "samsung,exynos5440-tmu", },
|
|
{ .compatible = "samsung,exynos7-tmu", },
|
|
{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, exynos_tmu_match);
|
|
|
|
static int exynos_of_get_soc_type(struct device_node *np)
|
|
{
|
|
if (of_device_is_compatible(np, "samsung,exynos3250-tmu"))
|
|
return SOC_ARCH_EXYNOS3250;
|
|
else if (of_device_is_compatible(np, "samsung,exynos4210-tmu"))
|
|
return SOC_ARCH_EXYNOS4210;
|
|
else if (of_device_is_compatible(np, "samsung,exynos4412-tmu"))
|
|
return SOC_ARCH_EXYNOS4412;
|
|
else if (of_device_is_compatible(np, "samsung,exynos5250-tmu"))
|
|
return SOC_ARCH_EXYNOS5250;
|
|
else if (of_device_is_compatible(np, "samsung,exynos5260-tmu"))
|
|
return SOC_ARCH_EXYNOS5260;
|
|
else if (of_device_is_compatible(np, "samsung,exynos5420-tmu"))
|
|
return SOC_ARCH_EXYNOS5420;
|
|
else if (of_device_is_compatible(np,
|
|
"samsung,exynos5420-tmu-ext-triminfo"))
|
|
return SOC_ARCH_EXYNOS5420_TRIMINFO;
|
|
else if (of_device_is_compatible(np, "samsung,exynos5433-tmu"))
|
|
return SOC_ARCH_EXYNOS5433;
|
|
else if (of_device_is_compatible(np, "samsung,exynos5440-tmu"))
|
|
return SOC_ARCH_EXYNOS5440;
|
|
else if (of_device_is_compatible(np, "samsung,exynos7-tmu"))
|
|
return SOC_ARCH_EXYNOS7;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int exynos_of_sensor_conf(struct device_node *np,
|
|
struct exynos_tmu_platform_data *pdata)
|
|
{
|
|
u32 value;
|
|
int ret;
|
|
|
|
of_node_get(np);
|
|
|
|
ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
|
|
pdata->gain = (u8)value;
|
|
of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
|
|
pdata->reference_voltage = (u8)value;
|
|
of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value);
|
|
pdata->noise_cancel_mode = (u8)value;
|
|
|
|
of_property_read_u32(np, "samsung,tmu_efuse_value",
|
|
&pdata->efuse_value);
|
|
of_property_read_u32(np, "samsung,tmu_min_efuse_value",
|
|
&pdata->min_efuse_value);
|
|
of_property_read_u32(np, "samsung,tmu_max_efuse_value",
|
|
&pdata->max_efuse_value);
|
|
|
|
of_property_read_u32(np, "samsung,tmu_first_point_trim", &value);
|
|
pdata->first_point_trim = (u8)value;
|
|
of_property_read_u32(np, "samsung,tmu_second_point_trim", &value);
|
|
pdata->second_point_trim = (u8)value;
|
|
of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value);
|
|
pdata->default_temp_offset = (u8)value;
|
|
|
|
of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
|
|
|
|
of_node_put(np);
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_map_dt_data(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct exynos_tmu_platform_data *pdata;
|
|
struct resource res;
|
|
|
|
if (!data || !pdev->dev.of_node)
|
|
return -ENODEV;
|
|
|
|
data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
|
|
if (data->id < 0)
|
|
data->id = 0;
|
|
|
|
data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
|
|
if (data->irq <= 0) {
|
|
dev_err(&pdev->dev, "failed to get IRQ\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
|
|
dev_err(&pdev->dev, "failed to get Resource 0\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
|
|
if (!data->base) {
|
|
dev_err(&pdev->dev, "Failed to ioremap memory\n");
|
|
return -EADDRNOTAVAIL;
|
|
}
|
|
|
|
pdata = devm_kzalloc(&pdev->dev,
|
|
sizeof(struct exynos_tmu_platform_data),
|
|
GFP_KERNEL);
|
|
if (!pdata)
|
|
return -ENOMEM;
|
|
|
|
exynos_of_sensor_conf(pdev->dev.of_node, pdata);
|
|
data->pdata = pdata;
|
|
data->soc = exynos_of_get_soc_type(pdev->dev.of_node);
|
|
|
|
switch (data->soc) {
|
|
case SOC_ARCH_EXYNOS4210:
|
|
data->tmu_initialize = exynos4210_tmu_initialize;
|
|
data->tmu_control = exynos4210_tmu_control;
|
|
data->tmu_read = exynos4210_tmu_read;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 4;
|
|
break;
|
|
case SOC_ARCH_EXYNOS3250:
|
|
case SOC_ARCH_EXYNOS4412:
|
|
case SOC_ARCH_EXYNOS5250:
|
|
case SOC_ARCH_EXYNOS5260:
|
|
case SOC_ARCH_EXYNOS5420:
|
|
case SOC_ARCH_EXYNOS5420_TRIMINFO:
|
|
data->tmu_initialize = exynos4412_tmu_initialize;
|
|
data->tmu_control = exynos4210_tmu_control;
|
|
data->tmu_read = exynos4412_tmu_read;
|
|
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 4;
|
|
break;
|
|
case SOC_ARCH_EXYNOS5433:
|
|
data->tmu_initialize = exynos5433_tmu_initialize;
|
|
data->tmu_control = exynos5433_tmu_control;
|
|
data->tmu_read = exynos4412_tmu_read;
|
|
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 8;
|
|
break;
|
|
case SOC_ARCH_EXYNOS5440:
|
|
data->tmu_initialize = exynos5440_tmu_initialize;
|
|
data->tmu_control = exynos5440_tmu_control;
|
|
data->tmu_read = exynos5440_tmu_read;
|
|
data->tmu_set_emulation = exynos5440_tmu_set_emulation;
|
|
data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
|
|
data->ntrip = 4;
|
|
break;
|
|
case SOC_ARCH_EXYNOS7:
|
|
data->tmu_initialize = exynos7_tmu_initialize;
|
|
data->tmu_control = exynos7_tmu_control;
|
|
data->tmu_read = exynos7_tmu_read;
|
|
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 8;
|
|
break;
|
|
default:
|
|
dev_err(&pdev->dev, "Platform not supported\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Check if the TMU shares some registers and then try to map the
|
|
* memory of common registers.
|
|
*/
|
|
if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
|
|
data->soc != SOC_ARCH_EXYNOS5440)
|
|
return 0;
|
|
|
|
if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
|
|
dev_err(&pdev->dev, "failed to get Resource 1\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
data->base_second = devm_ioremap(&pdev->dev, res.start,
|
|
resource_size(&res));
|
|
if (!data->base_second) {
|
|
dev_err(&pdev->dev, "Failed to ioremap memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct thermal_zone_of_device_ops exynos_sensor_ops = {
|
|
.get_temp = exynos_get_temp,
|
|
.set_emul_temp = exynos_tmu_set_emulation,
|
|
};
|
|
|
|
static int exynos_tmu_probe(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data;
|
|
int ret;
|
|
|
|
data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
|
|
GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
mutex_init(&data->lock);
|
|
|
|
/*
|
|
* Try enabling the regulator if found
|
|
* TODO: Add regulator as an SOC feature, so that regulator enable
|
|
* is a compulsory call.
|
|
*/
|
|
data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu");
|
|
if (!IS_ERR(data->regulator)) {
|
|
ret = regulator_enable(data->regulator);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to enable vtmu\n");
|
|
return ret;
|
|
}
|
|
} else {
|
|
if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
|
|
}
|
|
|
|
ret = exynos_map_dt_data(pdev);
|
|
if (ret)
|
|
goto err_sensor;
|
|
|
|
INIT_WORK(&data->irq_work, exynos_tmu_work);
|
|
|
|
data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
|
|
if (IS_ERR(data->clk)) {
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
|
ret = PTR_ERR(data->clk);
|
|
goto err_sensor;
|
|
}
|
|
|
|
data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
|
|
if (IS_ERR(data->clk_sec)) {
|
|
if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
|
|
dev_err(&pdev->dev, "Failed to get triminfo clock\n");
|
|
ret = PTR_ERR(data->clk_sec);
|
|
goto err_sensor;
|
|
}
|
|
} else {
|
|
ret = clk_prepare(data->clk_sec);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
|
goto err_sensor;
|
|
}
|
|
}
|
|
|
|
ret = clk_prepare(data->clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
|
goto err_clk_sec;
|
|
}
|
|
|
|
switch (data->soc) {
|
|
case SOC_ARCH_EXYNOS5433:
|
|
case SOC_ARCH_EXYNOS7:
|
|
data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
|
|
if (IS_ERR(data->sclk)) {
|
|
dev_err(&pdev->dev, "Failed to get sclk\n");
|
|
goto err_clk;
|
|
} else {
|
|
ret = clk_prepare_enable(data->sclk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to enable sclk\n");
|
|
goto err_clk;
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* data->tzd must be registered before calling exynos_tmu_initialize(),
|
|
* requesting irq and calling exynos_tmu_control().
|
|
*/
|
|
data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
|
|
&exynos_sensor_ops);
|
|
if (IS_ERR(data->tzd)) {
|
|
ret = PTR_ERR(data->tzd);
|
|
dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret);
|
|
goto err_sclk;
|
|
}
|
|
|
|
ret = exynos_tmu_initialize(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to initialize TMU\n");
|
|
goto err_thermal;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
|
|
IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
|
|
goto err_thermal;
|
|
}
|
|
|
|
exynos_tmu_control(pdev, true);
|
|
return 0;
|
|
|
|
err_thermal:
|
|
thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
|
|
err_sclk:
|
|
clk_disable_unprepare(data->sclk);
|
|
err_clk:
|
|
clk_unprepare(data->clk);
|
|
err_clk_sec:
|
|
if (!IS_ERR(data->clk_sec))
|
|
clk_unprepare(data->clk_sec);
|
|
err_sensor:
|
|
if (!IS_ERR(data->regulator))
|
|
regulator_disable(data->regulator);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int exynos_tmu_remove(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tzd = data->tzd;
|
|
|
|
thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
|
|
exynos_tmu_control(pdev, false);
|
|
|
|
clk_disable_unprepare(data->sclk);
|
|
clk_unprepare(data->clk);
|
|
if (!IS_ERR(data->clk_sec))
|
|
clk_unprepare(data->clk_sec);
|
|
|
|
if (!IS_ERR(data->regulator))
|
|
regulator_disable(data->regulator);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int exynos_tmu_suspend(struct device *dev)
|
|
{
|
|
exynos_tmu_control(to_platform_device(dev), false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_tmu_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
exynos_tmu_initialize(pdev);
|
|
exynos_tmu_control(pdev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
|
|
exynos_tmu_suspend, exynos_tmu_resume);
|
|
#define EXYNOS_TMU_PM (&exynos_tmu_pm)
|
|
#else
|
|
#define EXYNOS_TMU_PM NULL
|
|
#endif
|
|
|
|
static struct platform_driver exynos_tmu_driver = {
|
|
.driver = {
|
|
.name = "exynos-tmu",
|
|
.pm = EXYNOS_TMU_PM,
|
|
.of_match_table = exynos_tmu_match,
|
|
},
|
|
.probe = exynos_tmu_probe,
|
|
.remove = exynos_tmu_remove,
|
|
};
|
|
|
|
module_platform_driver(exynos_tmu_driver);
|
|
|
|
MODULE_DESCRIPTION("EXYNOS TMU Driver");
|
|
MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:exynos-tmu");
|