127 lines
4.5 KiB
C
127 lines
4.5 KiB
C
/*
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* Definitions for Marvell/Galileo EV-64260-BP Evaluation Board.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* The MV64x60 has 2 PCI buses each with 1 window from the CPU bus to
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* PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
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* We'll only use one PCI MEM window on each PCI bus.
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*
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* This is the CPU physical memory map (windows must be at least 1MB and start
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* on a boundary that is a multiple of the window size):
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*
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* 0xfc000000-0xffffffff - External FLASH on device module
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* 0xfbf00000-0xfbffffff - Embedded (on board) FLASH
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* 0xfbe00000-0xfbefffff - GT64260 Registers (preferably)
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* but really a config option
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* 0xfbd00000-0xfbdfffff - External SRAM on device module
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* 0xfbc00000-0xfbcfffff - TODC chip on device module
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* 0xfbb00000-0xfbbfffff - External UART on device module
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* 0xa2000000-0xfbafffff - <hole>
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* 0xa1000000-0xa1ffffff - PCI 1 I/O (defined in gt64260.h)
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* 0xa0000000-0xa0ffffff - PCI 0 I/O (defined in gt64260.h)
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* 0x90000000-0x9fffffff - PCI 1 MEM (defined in gt64260.h)
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* 0x80000000-0x8fffffff - PCI 0 MEM (defined in gt64260.h)
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*/
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#ifndef __PPC_PLATFORMS_EV64260_H
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#define __PPC_PLATFORMS_EV64260_H
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/* PCI mappings */
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#define EV64260_PCI0_IO_CPU_BASE 0xa0000000
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#define EV64260_PCI0_IO_PCI_BASE 0x00000000
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#define EV64260_PCI0_IO_SIZE 0x01000000
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#define EV64260_PCI0_MEM_CPU_BASE 0x80000000
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#define EV64260_PCI0_MEM_PCI_BASE 0x80000000
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#define EV64260_PCI0_MEM_SIZE 0x10000000
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#define EV64260_PCI1_IO_CPU_BASE (EV64260_PCI0_IO_CPU_BASE + \
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EV64260_PCI0_IO_SIZE)
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#define EV64260_PCI1_IO_PCI_BASE (EV64260_PCI0_IO_PCI_BASE + \
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EV64260_PCI0_IO_SIZE)
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#define EV64260_PCI1_IO_SIZE 0x01000000
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#define EV64260_PCI1_MEM_CPU_BASE (EV64260_PCI0_MEM_CPU_BASE + \
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EV64260_PCI0_MEM_SIZE)
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#define EV64260_PCI1_MEM_PCI_BASE (EV64260_PCI0_MEM_PCI_BASE + \
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EV64260_PCI0_MEM_SIZE)
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#define EV64260_PCI1_MEM_SIZE 0x10000000
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/* CPU Physical Memory Map setup (other than PCI) */
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#define EV64260_EXT_FLASH_BASE 0xfc000000
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#define EV64260_EMB_FLASH_BASE 0xfbf00000
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#define EV64260_EXT_SRAM_BASE 0xfbd00000
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#define EV64260_TODC_BASE 0xfbc00000
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#define EV64260_UART_BASE 0xfbb00000
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#define EV64260_EXT_FLASH_SIZE_ACTUAL 0x04000000 /* <= 64MB Extern FLASH */
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#define EV64260_EMB_FLASH_SIZE_ACTUAL 0x00080000 /* 512KB of Embed FLASH */
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#define EV64260_EXT_SRAM_SIZE_ACTUAL 0x00100000 /* 1MB SDRAM */
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#define EV64260_TODC_SIZE_ACTUAL 0x00000020 /* 32 bytes for TODC */
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#define EV64260_UART_SIZE_ACTUAL 0x00000040 /* 64 bytes for DUART */
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#define EV64260_EXT_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \
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EV64260_EXT_FLASH_SIZE_ACTUAL)
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#define EV64260_EMB_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \
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EV64260_EMB_FLASH_SIZE_ACTUAL)
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#define EV64260_EXT_SRAM_SIZE max(GT64260_WINDOW_SIZE_MIN, \
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EV64260_EXT_SRAM_SIZE_ACTUAL)
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#define EV64260_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \
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EV64260_TODC_SIZE_ACTUAL)
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/* Assembler in bootwrapper blows up if 'max' is used */
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#define EV64260_UART_SIZE GT64260_WINDOW_SIZE_MIN
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#define EV64260_UART_END ((EV64260_UART_BASE + \
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EV64260_UART_SIZE - 1) & 0xfff00000)
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/* Board-specific IRQ info */
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#define EV64260_UART_0_IRQ 85
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#define EV64260_UART_1_IRQ 86
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#define EV64260_PCI_0_IRQ 91
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#define EV64260_PCI_1_IRQ 93
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/* Serial port setup */
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#define EV64260_DEFAULT_BAUD 115200
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#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
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#define SERIAL_PORT_DFNS
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#define EV64260_MPSC_CLK_SRC 8 /* TCLK */
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#define EV64260_MPSC_CLK_FREQ 100000000 /* 100MHz clk */
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#else
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#define EV64260_SERIAL_0 (EV64260_UART_BASE + 0x20)
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#define EV64260_SERIAL_1 EV64260_UART_BASE
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#define BASE_BAUD (EV64260_DEFAULT_BAUD * 2)
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#ifdef CONFIG_SERIAL_MANY_PORTS
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#define RS_TABLE_SIZE 64
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#else
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#define RS_TABLE_SIZE 2
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#endif
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
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#endif
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/* Required for bootloader's ns16550.c code */
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#define STD_SERIAL_PORT_DFNS \
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{ 0, BASE_BAUD, EV64260_SERIAL_0, EV64260_UART_0_IRQ, STD_COM_FLAGS, \
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iomem_base: (u8 *)EV64260_SERIAL_0, /* ttyS0 */ \
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iomem_reg_shift: 2, \
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io_type: SERIAL_IO_MEM },
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#define SERIAL_PORT_DFNS \
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STD_SERIAL_PORT_DFNS
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#endif
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#endif /* __PPC_PLATFORMS_EV64260_H */
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