633 lines
16 KiB
C
633 lines
16 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/capability.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/export.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/byteorder.h>
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#include <asm/hv_driver.h>
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#include <hv/drv_pcie_rc_intf.h>
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/*
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* Initialization flow and process
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* -------------------------------
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*
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* This files contains the routines to search for PCI buses,
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* enumerate the buses, and configure any attached devices.
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*
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* There are two entry points here:
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* 1) tile_pci_init
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* This sets up the pci_controller structs, and opens the
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* FDs to the hypervisor. This is called from setup_arch() early
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* in the boot process.
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* 2) pcibios_init
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* This probes the PCI bus(es) for any attached hardware. It's
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* called by subsys_initcall. All of the real work is done by the
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* generic Linux PCI layer.
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*
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*/
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/*
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* This flag tells if the platform is TILEmpower that needs
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* special configuration for the PLX switch chip.
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*/
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int __write_once tile_plx_gen1;
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static struct pci_controller controllers[TILE_NUM_PCIE];
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static int num_controllers;
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static int pci_scan_flags[TILE_NUM_PCIE];
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static struct pci_ops tile_cfg_ops;
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/*
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* We don't need to worry about the alignment of resources.
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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/*
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* Open a FD to the hypervisor PCI device.
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*
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* controller_id is the controller number, config type is 0 or 1 for
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* config0 or config1 operations.
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*/
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static int __devinit tile_pcie_open(int controller_id, int config_type)
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{
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char filename[32];
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int fd;
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sprintf(filename, "pcie/%d/config%d", controller_id, config_type);
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fd = hv_dev_open((HV_VirtAddr)filename, 0);
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return fd;
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}
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/*
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* Get the IRQ numbers from the HV and set up the handlers for them.
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*/
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static int __devinit tile_init_irqs(int controller_id,
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struct pci_controller *controller)
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{
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char filename[32];
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int fd;
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int ret;
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int x;
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struct pcie_rc_config rc_config;
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sprintf(filename, "pcie/%d/ctl", controller_id);
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fd = hv_dev_open((HV_VirtAddr)filename, 0);
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if (fd < 0) {
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pr_err("PCI: hv_dev_open(%s) failed\n", filename);
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return -1;
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}
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ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
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sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
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hv_dev_close(fd);
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if (ret != sizeof(rc_config)) {
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pr_err("PCI: wanted %zd bytes, got %d\n",
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sizeof(rc_config), ret);
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return -1;
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}
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/* Record irq_base so that we can map INTx to IRQ # later. */
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controller->irq_base = rc_config.intr;
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for (x = 0; x < 4; x++)
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tile_irq_activate(rc_config.intr + x,
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TILE_IRQ_HW_CLEAR);
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if (rc_config.plx_gen1)
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controller->plx_gen1 = 1;
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return 0;
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}
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/*
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* First initialization entry point, called from setup_arch().
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*
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* Find valid controllers and fill in pci_controller structs for each
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* of them.
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*
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* Returns the number of controllers discovered.
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*/
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int __init tile_pci_init(void)
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{
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int i;
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pr_info("PCI: Searching for controllers...\n");
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/* Re-init number of PCIe controllers to support hot-plug feature. */
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num_controllers = 0;
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/* Do any configuration we need before using the PCIe */
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for (i = 0; i < TILE_NUM_PCIE; i++) {
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/*
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* To see whether we need a real config op based on
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* the results of pcibios_init(), to support PCIe hot-plug.
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*/
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if (pci_scan_flags[i] == 0) {
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int hv_cfg_fd0 = -1;
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int hv_cfg_fd1 = -1;
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int hv_mem_fd = -1;
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char name[32];
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struct pci_controller *controller;
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/*
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* Open the fd to the HV. If it fails then this
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* device doesn't exist.
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*/
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hv_cfg_fd0 = tile_pcie_open(i, 0);
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if (hv_cfg_fd0 < 0)
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continue;
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hv_cfg_fd1 = tile_pcie_open(i, 1);
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if (hv_cfg_fd1 < 0) {
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pr_err("PCI: Couldn't open config fd to HV "
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"for controller %d\n", i);
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goto err_cont;
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}
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sprintf(name, "pcie/%d/mem", i);
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hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
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if (hv_mem_fd < 0) {
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pr_err("PCI: Could not open mem fd to HV!\n");
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goto err_cont;
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}
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pr_info("PCI: Found PCI controller #%d\n", i);
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controller = &controllers[i];
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controller->index = i;
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controller->hv_cfg_fd[0] = hv_cfg_fd0;
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controller->hv_cfg_fd[1] = hv_cfg_fd1;
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controller->hv_mem_fd = hv_mem_fd;
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controller->first_busno = 0;
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controller->last_busno = 0xff;
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controller->ops = &tile_cfg_ops;
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num_controllers++;
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continue;
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err_cont:
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if (hv_cfg_fd0 >= 0)
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hv_dev_close(hv_cfg_fd0);
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if (hv_cfg_fd1 >= 0)
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hv_dev_close(hv_cfg_fd1);
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if (hv_mem_fd >= 0)
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hv_dev_close(hv_mem_fd);
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continue;
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}
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}
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/*
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* Before using the PCIe, see if we need to do any platform-specific
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* configuration, such as the PLX switch Gen 1 issue on TILEmpower.
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*/
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for (i = 0; i < num_controllers; i++) {
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struct pci_controller *controller = &controllers[i];
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if (controller->plx_gen1)
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tile_plx_gen1 = 1;
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}
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return num_controllers;
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}
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/*
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* (pin - 1) converts from the PCI standard's [1:4] convention to
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* a normal [0:3] range.
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*/
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static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pci_controller *controller =
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(struct pci_controller *)dev->sysdata;
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return (pin - 1) + controller->irq_base;
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}
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static void __devinit fixup_read_and_payload_sizes(void)
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{
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struct pci_dev *dev = NULL;
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int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
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int max_read_size = 0x2; /* Limit to 512 byte reads. */
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u16 new_values;
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/* Scan for the smallest maximum payload size. */
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
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int pcie_caps_offset;
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u32 devcap;
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int max_payload;
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pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (pcie_caps_offset == 0)
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continue;
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pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
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&devcap);
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max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
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if (max_payload < smallest_max_payload)
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smallest_max_payload = max_payload;
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}
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/* Now, set the max_payload_size for all devices to that value. */
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new_values = (max_read_size << 12) | (smallest_max_payload << 5);
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
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int pcie_caps_offset;
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u16 devctl;
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pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (pcie_caps_offset == 0)
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continue;
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pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
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&devctl);
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devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
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devctl |= new_values;
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pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
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devctl);
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}
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}
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/*
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* Second PCI initialization entry point, called by subsys_initcall.
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*
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* The controllers have been set up by the time we get here, by a call to
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* tile_pci_init.
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*/
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int __init pcibios_init(void)
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{
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int i;
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pr_info("PCI: Probing PCI hardware\n");
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/*
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* Delay a bit in case devices aren't ready. Some devices are
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* known to require at least 20ms here, but we use a more
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* conservative value.
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*/
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mdelay(250);
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/* Scan all of the recorded PCI controllers. */
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for (i = 0; i < TILE_NUM_PCIE; i++) {
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/*
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* Do real pcibios init ops if the controller is initialized
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* by tile_pci_init() successfully and not initialized by
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* pcibios_init() yet to support PCIe hot-plug.
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*/
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if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
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struct pci_controller *controller = &controllers[i];
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struct pci_bus *bus;
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if (tile_init_irqs(i, controller)) {
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pr_err("PCI: Could not initialize IRQs\n");
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continue;
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}
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pr_info("PCI: initializing controller #%d\n", i);
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/*
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* This comes from the generic Linux PCI driver.
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*
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* It reads the PCI tree for this bus into the Linux
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* data structures.
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*
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* This is inlined in linux/pci.h and calls into
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* pci_scan_bus_parented() in probe.c.
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*/
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bus = pci_scan_bus(0, controller->ops, controller);
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controller->root_bus = bus;
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controller->last_busno = bus->subordinate;
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}
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}
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/* Do machine dependent PCI interrupt routing */
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pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
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/*
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* This comes from the generic Linux PCI driver.
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*
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* It allocates all of the resources (I/O memory, etc)
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* associated with the devices read in above.
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*/
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pci_assign_unassigned_resources();
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/* Configure the max_read_size and max_payload_size values. */
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fixup_read_and_payload_sizes();
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/* Record the I/O resources in the PCI controller structure. */
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for (i = 0; i < TILE_NUM_PCIE; i++) {
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/*
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* Do real pcibios init ops if the controller is initialized
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* by tile_pci_init() successfully and not initialized by
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* pcibios_init() yet to support PCIe hot-plug.
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*/
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if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
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struct pci_bus *root_bus = controllers[i].root_bus;
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struct pci_bus *next_bus;
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struct pci_dev *dev;
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list_for_each_entry(dev, &root_bus->devices, bus_list) {
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/*
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* Find the PCI host controller, ie. the 1st
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* bridge.
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*/
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
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(PCI_SLOT(dev->devfn) == 0)) {
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next_bus = dev->subordinate;
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controllers[i].mem_resources[0] =
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*next_bus->resource[0];
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controllers[i].mem_resources[1] =
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*next_bus->resource[1];
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controllers[i].mem_resources[2] =
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*next_bus->resource[2];
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/* Setup flags. */
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pci_scan_flags[i] = 1;
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break;
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}
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}
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}
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}
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return 0;
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}
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subsys_initcall(pcibios_init);
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/*
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* No bus fixups needed.
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*/
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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/* Nothing needs to be done. */
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}
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void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling. */
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}
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/*
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* This can be called from the generic PCI layer, but doesn't need to
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* do anything.
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*/
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char __devinit *pcibios_setup(char *str)
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{
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/* Nothing needs to be done. */
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return str;
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}
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/*
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* This is called from the generic Linux layer.
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*/
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void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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/*
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* Enable memory and/or address decoding, as appropriate, for the
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* device described by the 'dev' struct.
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*
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* This is called from the generic PCI layer, and can be called
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* for bridges or endpoints.
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*/
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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u8 header_type;
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int i;
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struct resource *r;
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
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/*
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* For bridges, we enable both memory and I/O decoding
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* in call cases.
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*/
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cmd |= PCI_COMMAND_IO;
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cmd |= PCI_COMMAND_MEMORY;
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} else {
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/*
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* For endpoints, we enable memory and/or I/O decoding
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* only if they have a memory resource of that type.
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*/
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for (i = 0; i < 6; i++) {
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r = &dev->resource[i];
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if (r->flags & IORESOURCE_UNSET) {
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pr_err("PCI: Device %s not available "
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"because of resource collisions\n",
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pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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}
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/*
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* We only write the command if it changed.
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*/
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if (cmd != old_cmd)
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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return 0;
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}
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/****************************************************************
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*
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* Tile PCI config space read/write routines
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*
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****************************************************************/
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/*
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* These are the normal read and write ops
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* These are expanded with macros from pci_bus_read_config_byte() etc.
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*
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* devfn is the combined PCI slot & function.
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*
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* offset is in bytes, from the start of config space for the
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* specified bus & slot.
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*/
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static int __devinit tile_cfg_read(struct pci_bus *bus,
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unsigned int devfn,
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int offset,
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int size,
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u32 *val)
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{
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struct pci_controller *controller = bus->sysdata;
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int busnum = bus->number & 0xff;
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int slot = (devfn >> 3) & 0x1f;
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int function = devfn & 0x7;
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u32 addr;
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int config_mode = 1;
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/*
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* There is no bridge between the Tile and bus 0, so we
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* use config0 to talk to bus 0.
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*
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* If we're talking to a bus other than zero then we
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* must have found a bridge.
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*/
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if (busnum == 0) {
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/*
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* We fake an empty slot for (busnum == 0) && (slot > 0),
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* since there is only one slot on bus 0.
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*/
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if (slot) {
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*val = 0xFFFFFFFF;
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return 0;
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}
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config_mode = 0;
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}
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addr = busnum << 20; /* Bus in 27:20 */
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addr |= slot << 15; /* Slot (device) in 19:15 */
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addr |= function << 12; /* Function is in 14:12 */
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addr |= (offset & 0xFFF); /* byte address in 0:11 */
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return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
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(HV_VirtAddr)(val), size, addr);
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}
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/*
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* See tile_cfg_read() for relevant comments.
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* Note that "val" is the value to write, not a pointer to that value.
|
|
*/
|
|
static int __devinit tile_cfg_write(struct pci_bus *bus,
|
|
unsigned int devfn,
|
|
int offset,
|
|
int size,
|
|
u32 val)
|
|
{
|
|
struct pci_controller *controller = bus->sysdata;
|
|
int busnum = bus->number & 0xff;
|
|
int slot = (devfn >> 3) & 0x1f;
|
|
int function = devfn & 0x7;
|
|
u32 addr;
|
|
int config_mode = 1;
|
|
HV_VirtAddr valp = (HV_VirtAddr)&val;
|
|
|
|
/*
|
|
* For bus 0 slot 0 we use config 0 accesses.
|
|
*/
|
|
if (busnum == 0) {
|
|
/*
|
|
* We fake an empty slot for (busnum == 0) && (slot > 0),
|
|
* since there is only one slot on bus 0.
|
|
*/
|
|
if (slot)
|
|
return 0;
|
|
config_mode = 0;
|
|
}
|
|
|
|
addr = busnum << 20; /* Bus in 27:20 */
|
|
addr |= slot << 15; /* Slot (device) in 19:15 */
|
|
addr |= function << 12; /* Function is in 14:12 */
|
|
addr |= (offset & 0xFFF); /* byte address in 0:11 */
|
|
|
|
#ifdef __BIG_ENDIAN
|
|
/* Point to the correct part of the 32-bit "val". */
|
|
valp += 4 - size;
|
|
#endif
|
|
|
|
return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
|
|
valp, size, addr);
|
|
}
|
|
|
|
|
|
static struct pci_ops tile_cfg_ops = {
|
|
.read = tile_cfg_read,
|
|
.write = tile_cfg_write,
|
|
};
|
|
|
|
|
|
/*
|
|
* In the following, each PCI controller's mem_resources[1]
|
|
* represents its (non-prefetchable) PCI memory resource.
|
|
* mem_resources[0] and mem_resources[2] refer to its PCI I/O and
|
|
* prefetchable PCI memory resources, respectively.
|
|
* For more details, see pci_setup_bridge() in setup-bus.c.
|
|
* By comparing the target PCI memory address against the
|
|
* end address of controller 0, we can determine the controller
|
|
* that should accept the PCI memory access.
|
|
*/
|
|
#define TILE_READ(size, type) \
|
|
type _tile_read##size(unsigned long addr) \
|
|
{ \
|
|
type val; \
|
|
int idx = 0; \
|
|
if (addr > controllers[0].mem_resources[1].end && \
|
|
addr > controllers[0].mem_resources[2].end) \
|
|
idx = 1; \
|
|
if (hv_dev_pread(controllers[idx].hv_mem_fd, 0, \
|
|
(HV_VirtAddr)(&val), sizeof(type), addr)) \
|
|
pr_err("PCI: read %zd bytes at 0x%lX failed\n", \
|
|
sizeof(type), addr); \
|
|
return val; \
|
|
} \
|
|
EXPORT_SYMBOL(_tile_read##size)
|
|
|
|
TILE_READ(b, u8);
|
|
TILE_READ(w, u16);
|
|
TILE_READ(l, u32);
|
|
TILE_READ(q, u64);
|
|
|
|
#define TILE_WRITE(size, type) \
|
|
void _tile_write##size(type val, unsigned long addr) \
|
|
{ \
|
|
int idx = 0; \
|
|
if (addr > controllers[0].mem_resources[1].end && \
|
|
addr > controllers[0].mem_resources[2].end) \
|
|
idx = 1; \
|
|
if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0, \
|
|
(HV_VirtAddr)(&val), sizeof(type), addr)) \
|
|
pr_err("PCI: write %zd bytes at 0x%lX failed\n", \
|
|
sizeof(type), addr); \
|
|
} \
|
|
EXPORT_SYMBOL(_tile_write##size)
|
|
|
|
TILE_WRITE(b, u8);
|
|
TILE_WRITE(w, u16);
|
|
TILE_WRITE(l, u32);
|
|
TILE_WRITE(q, u64);
|