127 lines
4.2 KiB
C
127 lines
4.2 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __WL1271_SPI_H__
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#define __WL1271_SPI_H__
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#include "wl1271_reg.h"
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#define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0
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#define HW_PARTITION_REGISTERS_ADDR 0x1ffc0
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#define HW_PART0_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR)
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#define HW_PART0_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 4)
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#define HW_PART1_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 8)
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#define HW_PART1_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 12)
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#define HW_PART2_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 16)
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#define HW_PART2_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 20)
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#define HW_PART3_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 24)
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#define HW_ACCESS_REGISTER_SIZE 4
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#define HW_ACCESS_PRAM_MAX_RANGE 0x3c000
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#define WSPI_CMD_READ 0x40000000
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#define WSPI_CMD_WRITE 0x00000000
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#define WSPI_CMD_FIXED 0x20000000
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#define WSPI_CMD_BYTE_LENGTH 0x1FFE0000
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#define WSPI_CMD_BYTE_LENGTH_OFFSET 17
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#define WSPI_CMD_BYTE_ADDR 0x0001FFFF
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#define WSPI_INIT_CMD_CRC_LEN 5
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#define WSPI_INIT_CMD_START 0x00
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#define WSPI_INIT_CMD_TX 0x40
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/* the extra bypass bit is sampled by the TNET as '1' */
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#define WSPI_INIT_CMD_BYPASS_BIT 0x80
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#define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
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#define WSPI_INIT_CMD_EN_FIXEDBUSY 0x80
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#define WSPI_INIT_CMD_DIS_FIXEDBUSY 0x00
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#define WSPI_INIT_CMD_IOD 0x40
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#define WSPI_INIT_CMD_IP 0x20
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#define WSPI_INIT_CMD_CS 0x10
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#define WSPI_INIT_CMD_WS 0x08
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#define WSPI_INIT_CMD_WSPI 0x01
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#define WSPI_INIT_CMD_END 0x01
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#define WSPI_INIT_CMD_LEN 8
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#define HW_ACCESS_WSPI_FIXED_BUSY_LEN \
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((WL1271_BUSY_WORD_LEN - 4) / sizeof(u32))
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#define HW_ACCESS_WSPI_INIT_CMD_MASK 0
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#define OCP_CMD_LOOP 32
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#define OCP_CMD_WRITE 0x1
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#define OCP_CMD_READ 0x2
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#define OCP_READY_MASK BIT(18)
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#define OCP_STATUS_MASK (BIT(16) | BIT(17))
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#define OCP_STATUS_NO_RESP 0x00000
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#define OCP_STATUS_OK 0x10000
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#define OCP_STATUS_REQ_FAILED 0x20000
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#define OCP_STATUS_RESP_ERROR 0x30000
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/* Raw target IO, address is not translated */
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void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf,
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size_t len, bool fixed);
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void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf,
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size_t len, bool fixed);
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/* Translated target IO */
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void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
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bool fixed);
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void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
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bool fixed);
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u32 wl1271_spi_read32(struct wl1271 *wl, int addr);
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void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val);
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/* Top Register IO */
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void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val);
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u16 wl1271_top_reg_read(struct wl1271 *wl, int addr);
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/* INIT and RESET words */
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void wl1271_spi_reset(struct wl1271 *wl);
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void wl1271_spi_init(struct wl1271 *wl);
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int wl1271_set_partition(struct wl1271 *wl,
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struct wl1271_partition_set *p);
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static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr)
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{
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wl1271_spi_raw_read(wl, addr, &wl->buffer_32,
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sizeof(wl->buffer_32), false);
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return wl->buffer_32;
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}
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static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
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{
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wl->buffer_32 = val;
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wl1271_spi_raw_write(wl, addr, &wl->buffer_32,
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sizeof(wl->buffer_32), false);
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}
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#endif /* __WL1271_SPI_H__ */
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