503 lines
12 KiB
C
503 lines
12 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_cp.c
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*
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* Copyright (C) 2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/string.h>
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#include <linux/sysdev.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/amba/clcd.h>
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#include <linux/amba/mmci.h>
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#include <linux/io.h>
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#include <linux/gfp.h>
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#include <linux/clkdev.h>
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#include <linux/mtd/physmap.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/icst.h>
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#include <mach/cm.h>
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#include <mach/lm.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/timer-sp.h>
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#include <plat/clcd.h>
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#include <plat/fpga-irq.h>
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#include <plat/sched_clock.h>
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#include "common.h"
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#define INTCP_PA_FLASH_BASE 0x24000000
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#define INTCP_FLASH_SIZE SZ_32M
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#define INTCP_PA_CLCD_BASE 0xc0000000
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#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
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#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
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#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
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#define INTCP_ETH_SIZE 0x10
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#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
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#define INTCP_FLASHPROG 0x04
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#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
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#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
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/*
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* Logical Physical
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* f1000000 10000000 Core module registers
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* f1100000 11000000 System controller registers
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* f1200000 12000000 EBI registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* fc900000 c9000000 GPIO
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* fca00000 ca000000 SIC
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* fcb00000 cb000000 CP system control
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*/
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static struct map_desc intcp_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init intcp_map_io(void)
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{
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iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
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}
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static struct fpga_irq_data cic_irq_data = {
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.base = INTCP_VA_CIC_BASE,
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.irq_start = IRQ_CIC_START,
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.chip.name = "CIC",
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};
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static struct fpga_irq_data pic_irq_data = {
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.base = INTCP_VA_PIC_BASE,
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.irq_start = IRQ_PIC_START,
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.chip.name = "PIC",
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};
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static struct fpga_irq_data sic_irq_data = {
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.base = INTCP_VA_SIC_BASE,
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.irq_start = IRQ_SIC_START,
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.chip.name = "SIC",
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};
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static void __init intcp_init_irq(void)
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{
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u32 pic_mask, sic_mask;
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pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
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pic_mask |= (~((~0u) << (29 - 22))) << 22;
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sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
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/*
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* Disable all interrupt sources
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*/
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writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
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writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
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writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(-1, pic_mask, &pic_irq_data);
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fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)),
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&cic_irq_data);
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fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data);
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}
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/*
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* Clock handling
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*/
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#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
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#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
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static const struct icst_params cp_auxvco_params = {
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.ref = 24000000,
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.vco_max = ICST525_VCO_MAX_5V,
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.vco_min = ICST525_VCO_MIN,
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.vd_min = 8,
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.vd_max = 263,
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.rd_min = 3,
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.rd_max = 65,
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.s2div = icst525_s2div,
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.idx2s = icst525_idx2s,
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};
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static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
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{
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u32 val;
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val = readl(clk->vcoreg) & ~0x7ffff;
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val |= vco.v | (vco.r << 9) | (vco.s << 16);
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writel(0xa05f, CM_LOCK);
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writel(val, clk->vcoreg);
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writel(0, CM_LOCK);
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}
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static const struct clk_ops cp_auxclk_ops = {
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.round = icst_clk_round,
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.set = icst_clk_set,
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.setvco = cp_auxvco_set,
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};
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static struct clk cp_auxclk = {
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.ops = &cp_auxclk_ops,
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.params = &cp_auxvco_params,
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.vcoreg = CM_AUXOSC,
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};
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static struct clk sp804_clk = {
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.rate = 1000000,
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};
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static struct clk_lookup cp_lookups[] = {
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{ /* CLCD */
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.dev_id = "mb:c0",
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.clk = &cp_auxclk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.clk = &sp804_clk,
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},
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};
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/*
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* Flash handling.
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*/
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static int intcp_flash_init(struct platform_device *dev)
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{
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u32 val;
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val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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val |= CINTEGRATOR_FLASHPROG_FLWREN;
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writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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return 0;
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}
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static void intcp_flash_exit(struct platform_device *dev)
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{
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u32 val;
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val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
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writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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}
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static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
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{
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u32 val;
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val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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if (on)
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val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
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else
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val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
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writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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}
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static struct physmap_flash_data intcp_flash_data = {
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.width = 4,
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.init = intcp_flash_init,
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.exit = intcp_flash_exit,
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.set_vpp = intcp_flash_set_vpp,
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};
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static struct resource intcp_flash_resource = {
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.start = INTCP_PA_FLASH_BASE,
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.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device intcp_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &intcp_flash_data,
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},
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.num_resources = 1,
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.resource = &intcp_flash_resource,
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};
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = INTEGRATOR_CP_ETH_BASE,
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.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CP_ETHINT,
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.end = IRQ_CP_ETHINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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static struct platform_device *intcp_devs[] __initdata = {
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&intcp_flash_device,
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&smc91x_device,
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};
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/*
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* It seems that the card insertion interrupt remains active after
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* we've acknowledged it. We therefore ignore the interrupt, and
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* rely on reading it from the SIC. This also means that we must
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* clear the latched interrupt.
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*/
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static unsigned int mmc_status(struct device *dev)
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{
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unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
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writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
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return status & 8;
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}
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static struct mmci_platform_data mmc_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = mmc_status,
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.gpio_wp = -1,
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.gpio_cd = -1,
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};
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static struct amba_device mmc_device = {
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.dev = {
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.init_name = "mb:1c",
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.platform_data = &mmc_data,
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},
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.res = {
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.start = INTEGRATOR_CP_MMC_BASE,
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.end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
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.periphid = 0,
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};
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static struct amba_device aaci_device = {
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.dev = {
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.init_name = "mb:1d",
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},
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.res = {
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.start = INTEGRATOR_CP_AACI_BASE,
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.end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_CP_AACIINT, NO_IRQ },
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.periphid = 0,
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};
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/*
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* CLCD support
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*/
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/*
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* Ensure VGA is selected.
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*/
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static void cp_clcd_enable(struct clcd_fb *fb)
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{
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struct fb_var_screeninfo *var = &fb->fb.var;
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u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
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if (var->bits_per_pixel <= 8 ||
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(var->bits_per_pixel == 16 && var->green.length == 5))
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/* Pseudocolor, RGB555, BGR555 */
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val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
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else if (fb->fb.var.bits_per_pixel <= 16)
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/* truecolor RGB565 */
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val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
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else
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val = 0; /* no idea for this, don't trust the docs */
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cm_control(CM_CTRL_LCDMUXSEL_MASK|
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CM_CTRL_LCDEN0|
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CM_CTRL_LCDEN1|
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CM_CTRL_STATIC1|
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CM_CTRL_STATIC2|
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CM_CTRL_STATIC|
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CM_CTRL_n24BITEN, val);
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}
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static int cp_clcd_setup(struct clcd_fb *fb)
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{
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fb->panel = versatile_clcd_get_panel("VGA");
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if (!fb->panel)
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return -EINVAL;
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return versatile_clcd_setup_dma(fb, SZ_1M);
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}
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static struct clcd_board clcd_data = {
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.name = "Integrator/CP",
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.caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.enable = cp_clcd_enable,
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.setup = cp_clcd_setup,
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.mmap = versatile_clcd_mmap_dma,
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.remove = versatile_clcd_remove_dma,
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};
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static struct amba_device clcd_device = {
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.dev = {
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.init_name = "mb:c0",
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.coherent_dma_mask = ~0,
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.platform_data = &clcd_data,
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},
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.res = {
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.start = INTCP_PA_CLCD_BASE,
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.end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.dma_mask = ~0,
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.irq = { IRQ_CP_CLCDCINT, NO_IRQ },
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.periphid = 0,
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};
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static struct amba_device *amba_devs[] __initdata = {
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&mmc_device,
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&aaci_device,
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&clcd_device,
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};
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#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
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static void __init intcp_init_early(void)
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{
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clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
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integrator_init_early();
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#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
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versatile_sched_clock_init(REFCOUNTER, 24000000);
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#endif
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}
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static void __init intcp_init(void)
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{
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int i;
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platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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}
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#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
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#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
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#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
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static void __init intcp_timer_init(void)
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{
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
|
|
sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
|
|
}
|
|
|
|
static struct sys_timer cp_timer = {
|
|
.init = intcp_timer_init,
|
|
};
|
|
|
|
MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
|
|
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
|
|
.boot_params = 0x00000100,
|
|
.reserve = integrator_reserve,
|
|
.map_io = intcp_map_io,
|
|
.init_early = intcp_init_early,
|
|
.init_irq = intcp_init_irq,
|
|
.timer = &cp_timer,
|
|
.init_machine = intcp_init,
|
|
MACHINE_END
|