442 lines
10 KiB
C
442 lines
10 KiB
C
/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
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*
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* Copyright (c) 2007, 2010 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2443 Clock control suport - common code
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*/
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/regs-s3c2443-clock.h>
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#include <plat/s3c2443.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq.h>
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static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
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{
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u32 ctrlbit = clk->ctrlbit;
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u32 con = __raw_readl(reg);
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if (enable)
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con |= ctrlbit;
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else
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con &= ~ctrlbit;
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__raw_writel(con, reg);
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return 0;
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}
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int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
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}
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int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
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}
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int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
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}
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/* mpllref is a direct descendant of clk_xtal by default, but it is not
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* elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
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* such directly equating the two source clocks is impossible.
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*/
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struct clk clk_mpllref = {
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.name = "mpllref",
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.parent = &clk_xtal,
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};
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static struct clk *clk_epllref_sources[] = {
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[0] = &clk_mpllref,
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[1] = &clk_mpllref,
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[2] = &clk_xtal,
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[3] = &clk_ext,
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};
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struct clksrc_clk clk_epllref = {
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.clk = {
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.name = "epllref",
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_epllref_sources,
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.nr_sources = ARRAY_SIZE(clk_epllref_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
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};
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/* esysclk
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*
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* this is sourced from either the EPLL or the EPLLref clock
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*/
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static struct clk *clk_sysclk_sources[] = {
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[0] = &clk_epllref.clk,
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[1] = &clk_epll,
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};
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struct clksrc_clk clk_esysclk = {
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.clk = {
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.name = "esysclk",
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.parent = &clk_epll,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_sysclk_sources,
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.nr_sources = ARRAY_SIZE(clk_sysclk_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
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};
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static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long div = __raw_readl(S3C2443_CLKDIV0);
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div &= S3C2443_CLKDIV0_EXTDIV_MASK;
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div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
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return parent_rate / (div + 1);
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}
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static struct clk clk_mdivclk = {
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.name = "mdivclk",
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.parent = &clk_mpllref,
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.ops = &(struct clk_ops) {
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.get_rate = s3c2443_getrate_mdivclk,
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},
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};
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static struct clk *clk_msysclk_sources[] = {
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[0] = &clk_mpllref,
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[1] = &clk_mpll,
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[2] = &clk_mdivclk,
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[3] = &clk_mpllref,
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};
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struct clksrc_clk clk_msysclk = {
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.clk = {
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.name = "msysclk",
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.parent = &clk_xtal,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_msysclk_sources,
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.nr_sources = ARRAY_SIZE(clk_msysclk_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
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};
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/* prediv
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*
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* this divides the msysclk down to pass to h/p/etc.
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*/
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static unsigned long s3c2443_prediv_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
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clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
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return rate / (clkdiv0 + 1);
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}
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static struct clk clk_prediv = {
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.name = "prediv",
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.parent = &clk_msysclk.clk,
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.ops = &(struct clk_ops) {
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.get_rate = s3c2443_prediv_getrate,
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},
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};
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/* usbhost
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*
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* usb host bus-clock, usually 48MHz to provide USB bus clock timing
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*/
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static struct clksrc_clk clk_usb_bus_host = {
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.clk = {
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.name = "usb-bus-host-parent",
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.parent = &clk_esysclk.clk,
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.ctrlbit = S3C2443_SCLKCON_USBHOST,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
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};
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/* common clksrc clocks */
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static struct clksrc_clk clksrc_clks[] = {
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{
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/* ART baud-rate clock sourced from esysclk via a divisor */
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.clk = {
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.name = "uartclk",
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
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}, {
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/* camera interface bus-clock, divided down from esysclk */
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.clk = {
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.name = "camif-upll", /* same as 2440 name */
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.parent = &clk_esysclk.clk,
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.ctrlbit = S3C2443_SCLKCON_CAMCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
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}, {
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.clk = {
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.name = "display-if",
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.parent = &clk_esysclk.clk,
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.ctrlbit = S3C2443_SCLKCON_DISPCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
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},
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};
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static struct clk init_clocks_off[] = {
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{
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.name = "adc",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_ADC,
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}, {
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.name = "i2c",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIC,
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}
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};
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static struct clk init_clocks[] = {
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{
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA0,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA1,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA2,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA3,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA4,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA5,
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}, {
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.name = "hsmmc",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_HSMMC,
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}, {
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.name = "gpio",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_GPIO,
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}, {
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.name = "usb-host",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_USBH,
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}, {
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.name = "usb-device",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_USBD,
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}, {
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.name = "lcd",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_LCDC,
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}, {
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.name = "timers",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_PWMT,
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}, {
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.name = "cfc",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_CFC,
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}, {
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.name = "ssmc",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_SSMC,
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}, {
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.name = "uart",
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.devname = "s3c2440-uart.0",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_UART0,
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}, {
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.name = "uart",
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.devname = "s3c2440-uart.1",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_UART1,
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}, {
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.name = "uart",
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.devname = "s3c2440-uart.2",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_UART2,
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}, {
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.name = "uart",
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.devname = "s3c2440-uart.3",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_UART3,
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}, {
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.name = "rtc",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_RTC,
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}, {
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.name = "watchdog",
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.parent = &clk_p,
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.ctrlbit = S3C2443_PCLKCON_WDT,
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}, {
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.name = "ac97",
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.parent = &clk_p,
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.ctrlbit = S3C2443_PCLKCON_AC97,
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}, {
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.name = "nand",
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.parent = &clk_h,
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}, {
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.name = "usb-bus-host",
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.parent = &clk_usb_bus_host.clk,
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}
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};
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static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
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{
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clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
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return clkcon0 + 1;
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}
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/* EPLLCON compatible enough to get on/off information */
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void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
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fdiv_fn get_fdiv)
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{
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unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
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unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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struct clk *xtal_clk;
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unsigned long xtal;
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unsigned long pll;
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unsigned long fclk;
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unsigned long hclk;
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unsigned long pclk;
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int ptr;
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xtal_clk = clk_get(NULL, "xtal");
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xtal = clk_get_rate(xtal_clk);
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clk_put(xtal_clk);
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pll = get_mpll(mpllcon, xtal);
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clk_msysclk.clk.rate = pll;
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fclk = pll / get_fdiv(clkdiv0);
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hclk = s3c2443_prediv_getrate(&clk_prediv);
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hclk /= s3c2443_get_hdiv(clkdiv0);
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pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
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s3c24xx_setup_clocks(fclk, hclk, pclk);
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printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
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(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
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print_mhz(pll), print_mhz(fclk),
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print_mhz(hclk), print_mhz(pclk));
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for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
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s3c_set_clksrc(&clksrc_clks[ptr], true);
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/* ensure usb bus clock is within correct rate of 48MHz */
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if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
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printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
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clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
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}
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printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
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(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
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print_mhz(clk_get_rate(&clk_epll)),
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print_mhz(clk_get_rate(&clk_usb_bus)));
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}
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static struct clk *clks[] __initdata = {
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&clk_prediv,
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&clk_mpllref,
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&clk_mdivclk,
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&clk_ext,
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&clk_epll,
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&clk_usb_bus,
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};
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static struct clksrc_clk *clksrcs[] __initdata = {
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&clk_usb_bus_host,
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&clk_epllref,
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&clk_esysclk,
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&clk_msysclk,
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};
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void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
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fdiv_fn get_fdiv)
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{
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int ptr;
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/* s3c2443 parents h and p clocks from prediv */
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clk_h.parent = &clk_prediv;
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clk_p.parent = &clk_prediv;
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clk_usb_bus.parent = &clk_usb_bus_host.clk;
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clk_epll.parent = &clk_epllref.clk;
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s3c24xx_register_baseclocks(xtal);
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s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_register_clksrc(clksrcs[ptr], 1);
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s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
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s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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/* See s3c2443/etc notes on disabling clocks at init time */
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c2443_common_setup_clocks(get_mpll, get_fdiv);
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}
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