95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/*
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* arch/xtensa/kernel/pci-dma.c
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*
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* DMA coherent memory allocation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Copyright (C) 2002 - 2005 Tensilica Inc.
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*
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* Based on version for i386.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/gfp.h>
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#include <asm/io.h>
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#include <asm/cacheflush.h>
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/*
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* Note: We assume that the full memory space is always mapped to 'kseg'
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* Otherwise we have to use page attributes (not implemented).
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*/
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void *
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dma_alloc_coherent(struct device *dev,size_t size,dma_addr_t *handle,gfp_t flag)
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{
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unsigned long ret;
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unsigned long uncached = 0;
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/* ignore region speicifiers */
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flag &= ~(__GFP_DMA | __GFP_HIGHMEM);
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if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
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flag |= GFP_DMA;
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ret = (unsigned long)__get_free_pages(flag, get_order(size));
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if (ret == 0)
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return NULL;
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/* We currently don't support coherent memory outside KSEG */
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if (ret < XCHAL_KSEG_CACHED_VADDR
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|| ret >= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE)
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BUG();
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if (ret != 0) {
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memset((void*) ret, 0, size);
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uncached = ret+XCHAL_KSEG_BYPASS_VADDR-XCHAL_KSEG_CACHED_VADDR;
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*handle = virt_to_bus((void*)ret);
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__flush_invalidate_dcache_range(ret, size);
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}
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return (void*)uncached;
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}
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void dma_free_coherent(struct device *hwdev, size_t size,
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void *vaddr, dma_addr_t dma_handle)
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{
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long addr=(long)vaddr+XCHAL_KSEG_CACHED_VADDR-XCHAL_KSEG_BYPASS_VADDR;
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if (addr < 0 || addr >= XCHAL_KSEG_SIZE)
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BUG();
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free_pages(addr, get_order(size));
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}
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void consistent_sync(void *vaddr, size_t size, int direction)
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{
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switch (direction) {
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case PCI_DMA_NONE:
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BUG();
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case PCI_DMA_FROMDEVICE: /* invalidate only */
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__invalidate_dcache_range((unsigned long)vaddr,
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(unsigned long)size);
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break;
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case PCI_DMA_TODEVICE: /* writeback only */
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case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */
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__flush_invalidate_dcache_range((unsigned long)vaddr,
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(unsigned long)size);
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break;
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}
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}
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