133 lines
3.7 KiB
Plaintext
133 lines
3.7 KiB
Plaintext
* STM32 GPIO and Pin Mux/Config controller
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STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
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controller. It controls the input/output settings on the available pins and
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also provides ability to multiplex and configure the output of various on-chip
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controllers onto these pads.
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Pin controller node:
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Required properies:
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- compatible: value should be one of the following:
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(a) "st,stm32f429-pinctrl"
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(b) "st,stm32f746-pinctrl"
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- #address-cells: The value of this property must be 1
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- #size-cells : The value of this property must be 1
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- ranges : defines mapping between pin controller node (parent) to
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gpio-bank node (children).
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- interrupt-parent: phandle of the interrupt parent to which the external
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GPIO interrupts are forwarded to.
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- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
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which includes IRQ mux selection register, and the offset of the IRQ mux
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selection register.
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- pins-are-numbered: Specify the subnodes are using numbered pinmux to
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specify pins.
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GPIO controller/bank node:
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Required properties:
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- gpio-controller : Indicates this device is a GPIO controller
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- #gpio-cells : Should be two.
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The first cell is the pin number
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The second one is the polarity:
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- 0 for active high
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- 1 for active low
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- reg : The gpio address range, relative to the pinctrl range
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- clocks : clock that drives this bank
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- st,bank-name : Should be a name string for this bank as specified in
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the datasheet
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Optional properties:
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- reset: : Reference to the reset controller
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Example:
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#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
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...
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pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32f429-pinctrl";
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ranges = <0 0x40020000 0x3000>;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0x400>;
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resets = <&reset_ahb1 0>;
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st,bank-name = "GPIOA";
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};
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...
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pin-functions nodes follow...
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};
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Contents of function subnode node:
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----------------------------------
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Subnode format
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A pinctrl node should contain at least one subnode representing the
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pinctrl group available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive, output high/low and output speed.
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node {
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pinmux = <PIN_NUMBER_PINMUX>;
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GENERIC_PINCONFIG;
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};
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Required properties:
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- pinmux: integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are defined in
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dt-bindings/pinctrl/<soc>-pinfunc.h directly.
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These defines are calculated as:
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((port * 16 + line) << 8) | function
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With:
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- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
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- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
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- function: The function number, can be:
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* 0 : GPIO
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* 1 : Alternate Function 0
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* 2 : Alternate Function 1
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* 3 : Alternate Function 2
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* ...
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* 16 : Alternate Function 15
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* 17 : Analog
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Optional properties:
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- GENERIC_PINCONFIG: is the generic pinconfig options to use.
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Available options are:
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- bias-disable,
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- bias-pull-down,
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- bias-pull-up,
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- drive-push-pull,
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- drive-open-drain,
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- output-low
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- output-high
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- slew-rate = <x>, with x being:
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< 0 > : Low speed
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< 1 > : Medium speed
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< 2 > : Fast speed
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< 3 > : High speed
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Example:
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pin-controller {
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...
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
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bias-disable;
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};
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};
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};
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&usart1 {
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pinctrl-0 = <&usart1_pins_a>;
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pinctrl-names = "default";
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status = "okay";
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};
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