1989 lines
50 KiB
C
1989 lines
50 KiB
C
/*
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* drivers/soc/tegra/pmc.c
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*
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* Copyright (c) 2010 Google, Inc
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define pr_fmt(fmt) "tegra-pmc: " fmt
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_clk.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/reboot.h>
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#include <linux/reset.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pmc.h>
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#define PMC_CNTRL 0x0
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#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
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#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
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#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
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#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
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#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
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#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
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#define PMC_CNTRL_MAIN_RST BIT(4)
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#define DPD_SAMPLE 0x020
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#define DPD_SAMPLE_ENABLE BIT(0)
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#define DPD_SAMPLE_DISABLE (0 << 0)
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#define PWRGATE_TOGGLE 0x30
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#define PWRGATE_TOGGLE_START BIT(8)
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#define REMOVE_CLAMPING 0x34
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#define PWRGATE_STATUS 0x38
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#define PMC_PWR_DET 0x48
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#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
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#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
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#define PMC_SCRATCH0_MODE_RCM BIT(1)
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#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
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PMC_SCRATCH0_MODE_BOOTLOADER | \
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PMC_SCRATCH0_MODE_RCM)
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#define PMC_CPUPWRGOOD_TIMER 0xc8
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#define PMC_CPUPWROFF_TIMER 0xcc
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#define PMC_PWR_DET_VALUE 0xe4
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#define PMC_SCRATCH41 0x140
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#define PMC_SENSOR_CTRL 0x1b0
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#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
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#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
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#define PMC_RST_STATUS 0x1b4
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#define PMC_RST_STATUS_POR 0
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#define PMC_RST_STATUS_WATCHDOG 1
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#define PMC_RST_STATUS_SENSOR 2
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#define PMC_RST_STATUS_SW_MAIN 3
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#define PMC_RST_STATUS_LP0 4
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#define PMC_RST_STATUS_AOTAG 5
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#define IO_DPD_REQ 0x1b8
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#define IO_DPD_REQ_CODE_IDLE (0U << 30)
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#define IO_DPD_REQ_CODE_OFF (1U << 30)
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#define IO_DPD_REQ_CODE_ON (2U << 30)
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#define IO_DPD_REQ_CODE_MASK (3U << 30)
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#define IO_DPD_STATUS 0x1bc
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#define IO_DPD2_REQ 0x1c0
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#define IO_DPD2_STATUS 0x1c4
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#define SEL_DPD_TIM 0x1c8
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#define PMC_SCRATCH54 0x258
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#define PMC_SCRATCH54_DATA_SHIFT 8
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#define PMC_SCRATCH54_ADDR_SHIFT 0
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#define PMC_SCRATCH55 0x25c
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#define PMC_SCRATCH55_RESET_TEGRA BIT(31)
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#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
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#define PMC_SCRATCH55_PINMUX_SHIFT 24
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#define PMC_SCRATCH55_16BITOP BIT(15)
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#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
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#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
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#define GPU_RG_CNTRL 0x2d4
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/* Tegra186 and later */
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#define WAKE_AOWAKE_CTRL 0x4f4
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#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
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struct tegra_powergate {
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struct generic_pm_domain genpd;
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struct tegra_pmc *pmc;
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unsigned int id;
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struct clk **clks;
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unsigned int num_clks;
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struct reset_control *reset;
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};
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struct tegra_io_pad_soc {
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enum tegra_io_pad id;
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unsigned int dpd;
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unsigned int voltage;
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};
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struct tegra_pmc_regs {
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unsigned int scratch0;
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unsigned int dpd_req;
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unsigned int dpd_status;
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unsigned int dpd2_req;
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unsigned int dpd2_status;
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};
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struct tegra_pmc_soc {
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unsigned int num_powergates;
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const char *const *powergates;
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unsigned int num_cpu_powergates;
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const u8 *cpu_powergates;
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bool has_tsense_reset;
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bool has_gpu_clamps;
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bool needs_mbist_war;
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const struct tegra_io_pad_soc *io_pads;
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unsigned int num_io_pads;
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const struct tegra_pmc_regs *regs;
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void (*init)(struct tegra_pmc *pmc);
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void (*setup_irq_polarity)(struct tegra_pmc *pmc,
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struct device_node *np,
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bool invert);
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};
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/**
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* struct tegra_pmc - NVIDIA Tegra PMC
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* @dev: pointer to PMC device structure
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* @base: pointer to I/O remapped register region
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* @clk: pointer to pclk clock
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* @soc: pointer to SoC data structure
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* @debugfs: pointer to debugfs entry
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* @rate: currently configured rate of pclk
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* @suspend_mode: lowest suspend mode available
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* @cpu_good_time: CPU power good time (in microseconds)
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* @cpu_off_time: CPU power off time (in microsecends)
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* @core_osc_time: core power good OSC time (in microseconds)
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* @core_pmu_time: core power good PMU time (in microseconds)
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* @core_off_time: core power off time (in microseconds)
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* @corereq_high: core power request is active-high
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* @sysclkreq_high: system clock request is active-high
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* @combined_req: combined power request for CPU & core
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* @cpu_pwr_good_en: CPU power good signal is enabled
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* @lp0_vec_phys: physical base address of the LP0 warm boot code
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* @lp0_vec_size: size of the LP0 warm boot code
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* @powergates_available: Bitmap of available power gates
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* @powergates_lock: mutex for power gate register access
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*/
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struct tegra_pmc {
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struct device *dev;
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void __iomem *base;
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void __iomem *wake;
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void __iomem *aotag;
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void __iomem *scratch;
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struct clk *clk;
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struct dentry *debugfs;
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const struct tegra_pmc_soc *soc;
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unsigned long rate;
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enum tegra_suspend_mode suspend_mode;
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u32 cpu_good_time;
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u32 cpu_off_time;
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u32 core_osc_time;
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u32 core_pmu_time;
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u32 core_off_time;
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bool corereq_high;
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bool sysclkreq_high;
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bool combined_req;
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bool cpu_pwr_good_en;
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u32 lp0_vec_phys;
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u32 lp0_vec_size;
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DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
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struct mutex powergates_lock;
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};
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static struct tegra_pmc *pmc = &(struct tegra_pmc) {
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.base = NULL,
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.suspend_mode = TEGRA_SUSPEND_NONE,
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};
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static inline struct tegra_powergate *
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to_powergate(struct generic_pm_domain *domain)
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{
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return container_of(domain, struct tegra_powergate, genpd);
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}
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static u32 tegra_pmc_readl(unsigned long offset)
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{
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return readl(pmc->base + offset);
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}
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static void tegra_pmc_writel(u32 value, unsigned long offset)
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{
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writel(value, pmc->base + offset);
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}
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static inline bool tegra_powergate_state(int id)
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{
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if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
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return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
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else
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return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
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}
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static inline bool tegra_powergate_is_valid(int id)
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{
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return (pmc->soc && pmc->soc->powergates[id]);
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}
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static inline bool tegra_powergate_is_available(int id)
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{
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return test_bit(id, pmc->powergates_available);
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}
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static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
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{
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unsigned int i;
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if (!pmc || !pmc->soc || !name)
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return -EINVAL;
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for (i = 0; i < pmc->soc->num_powergates; i++) {
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if (!tegra_powergate_is_valid(i))
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continue;
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if (!strcmp(name, pmc->soc->powergates[i]))
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return i;
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}
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return -ENODEV;
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}
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/**
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* tegra_powergate_set() - set the state of a partition
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* @id: partition ID
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* @new_state: new state of the partition
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*/
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static int tegra_powergate_set(unsigned int id, bool new_state)
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{
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bool status;
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int err;
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if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
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return -EINVAL;
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mutex_lock(&pmc->powergates_lock);
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if (tegra_powergate_state(id) == new_state) {
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mutex_unlock(&pmc->powergates_lock);
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return 0;
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}
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tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
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err = readx_poll_timeout(tegra_powergate_state, id, status,
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status == new_state, 10, 100000);
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mutex_unlock(&pmc->powergates_lock);
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return err;
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}
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static int __tegra_powergate_remove_clamping(unsigned int id)
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{
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u32 mask;
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mutex_lock(&pmc->powergates_lock);
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/*
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* On Tegra124 and later, the clamps for the GPU are controlled by a
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* separate register (with different semantics).
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*/
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if (id == TEGRA_POWERGATE_3D) {
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if (pmc->soc->has_gpu_clamps) {
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tegra_pmc_writel(0, GPU_RG_CNTRL);
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goto out;
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}
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}
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/*
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* Tegra 2 has a bug where PCIE and VDE clamping masks are
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* swapped relatively to the partition ids
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*/
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if (id == TEGRA_POWERGATE_VDEC)
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mask = (1 << TEGRA_POWERGATE_PCIE);
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else if (id == TEGRA_POWERGATE_PCIE)
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mask = (1 << TEGRA_POWERGATE_VDEC);
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else
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mask = (1 << id);
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tegra_pmc_writel(mask, REMOVE_CLAMPING);
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out:
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mutex_unlock(&pmc->powergates_lock);
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return 0;
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}
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static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
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{
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unsigned int i;
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for (i = 0; i < pg->num_clks; i++)
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clk_disable_unprepare(pg->clks[i]);
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}
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static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
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{
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unsigned int i;
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int err;
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for (i = 0; i < pg->num_clks; i++) {
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err = clk_prepare_enable(pg->clks[i]);
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if (err)
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goto out;
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}
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return 0;
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out:
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while (i--)
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clk_disable_unprepare(pg->clks[i]);
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return err;
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}
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int __weak tegra210_clk_handle_mbist_war(unsigned int id)
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{
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return 0;
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}
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static int tegra_powergate_power_up(struct tegra_powergate *pg,
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bool disable_clocks)
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{
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int err;
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err = reset_control_assert(pg->reset);
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if (err)
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return err;
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usleep_range(10, 20);
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err = tegra_powergate_set(pg->id, true);
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if (err < 0)
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return err;
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usleep_range(10, 20);
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err = tegra_powergate_enable_clocks(pg);
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if (err)
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goto disable_clks;
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usleep_range(10, 20);
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err = __tegra_powergate_remove_clamping(pg->id);
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if (err)
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goto disable_clks;
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usleep_range(10, 20);
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err = reset_control_deassert(pg->reset);
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if (err)
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goto powergate_off;
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usleep_range(10, 20);
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if (pg->pmc->soc->needs_mbist_war)
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err = tegra210_clk_handle_mbist_war(pg->id);
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if (err)
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goto disable_clks;
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if (disable_clocks)
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tegra_powergate_disable_clocks(pg);
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return 0;
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disable_clks:
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tegra_powergate_disable_clocks(pg);
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usleep_range(10, 20);
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powergate_off:
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tegra_powergate_set(pg->id, false);
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return err;
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}
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static int tegra_powergate_power_down(struct tegra_powergate *pg)
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{
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int err;
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err = tegra_powergate_enable_clocks(pg);
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if (err)
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return err;
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usleep_range(10, 20);
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err = reset_control_assert(pg->reset);
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if (err)
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goto disable_clks;
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usleep_range(10, 20);
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tegra_powergate_disable_clocks(pg);
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usleep_range(10, 20);
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err = tegra_powergate_set(pg->id, false);
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if (err)
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goto assert_resets;
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return 0;
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assert_resets:
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tegra_powergate_enable_clocks(pg);
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usleep_range(10, 20);
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reset_control_deassert(pg->reset);
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usleep_range(10, 20);
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disable_clks:
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tegra_powergate_disable_clocks(pg);
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return err;
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}
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static int tegra_genpd_power_on(struct generic_pm_domain *domain)
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{
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struct tegra_powergate *pg = to_powergate(domain);
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int err;
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err = tegra_powergate_power_up(pg, true);
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if (err)
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pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
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err);
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return err;
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}
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static int tegra_genpd_power_off(struct generic_pm_domain *domain)
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{
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struct tegra_powergate *pg = to_powergate(domain);
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int err;
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err = tegra_powergate_power_down(pg);
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if (err)
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pr_err("failed to turn off PM domain %s: %d\n",
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pg->genpd.name, err);
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return err;
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}
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/**
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* tegra_powergate_power_on() - power on partition
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* @id: partition ID
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*/
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int tegra_powergate_power_on(unsigned int id)
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{
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if (!tegra_powergate_is_available(id))
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return -EINVAL;
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return tegra_powergate_set(id, true);
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}
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/**
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* tegra_powergate_power_off() - power off partition
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* @id: partition ID
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*/
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int tegra_powergate_power_off(unsigned int id)
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{
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if (!tegra_powergate_is_available(id))
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return -EINVAL;
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return tegra_powergate_set(id, false);
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}
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EXPORT_SYMBOL(tegra_powergate_power_off);
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/**
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* tegra_powergate_is_powered() - check if partition is powered
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* @id: partition ID
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*/
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int tegra_powergate_is_powered(unsigned int id)
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{
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int status;
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if (!tegra_powergate_is_valid(id))
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&pmc->powergates_lock);
|
|
status = tegra_powergate_state(id);
|
|
mutex_unlock(&pmc->powergates_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* tegra_powergate_remove_clamping() - remove power clamps for partition
|
|
* @id: partition ID
|
|
*/
|
|
int tegra_powergate_remove_clamping(unsigned int id)
|
|
{
|
|
if (!tegra_powergate_is_available(id))
|
|
return -EINVAL;
|
|
|
|
return __tegra_powergate_remove_clamping(id);
|
|
}
|
|
EXPORT_SYMBOL(tegra_powergate_remove_clamping);
|
|
|
|
/**
|
|
* tegra_powergate_sequence_power_up() - power up partition
|
|
* @id: partition ID
|
|
* @clk: clock for partition
|
|
* @rst: reset for partition
|
|
*
|
|
* Must be called with clk disabled, and returns with clk enabled.
|
|
*/
|
|
int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
|
|
struct reset_control *rst)
|
|
{
|
|
struct tegra_powergate *pg;
|
|
int err;
|
|
|
|
if (!tegra_powergate_is_available(id))
|
|
return -EINVAL;
|
|
|
|
pg = kzalloc(sizeof(*pg), GFP_KERNEL);
|
|
if (!pg)
|
|
return -ENOMEM;
|
|
|
|
pg->id = id;
|
|
pg->clks = &clk;
|
|
pg->num_clks = 1;
|
|
pg->reset = rst;
|
|
pg->pmc = pmc;
|
|
|
|
err = tegra_powergate_power_up(pg, false);
|
|
if (err)
|
|
pr_err("failed to turn on partition %d: %d\n", id, err);
|
|
|
|
kfree(pg);
|
|
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
|
|
|
|
#ifdef CONFIG_SMP
|
|
/**
|
|
* tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
|
|
* @cpuid: CPU partition ID
|
|
*
|
|
* Returns the partition ID corresponding to the CPU partition ID or a
|
|
* negative error code on failure.
|
|
*/
|
|
static int tegra_get_cpu_powergate_id(unsigned int cpuid)
|
|
{
|
|
if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
|
|
return pmc->soc->cpu_powergates[cpuid];
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/**
|
|
* tegra_pmc_cpu_is_powered() - check if CPU partition is powered
|
|
* @cpuid: CPU partition ID
|
|
*/
|
|
bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
|
|
{
|
|
int id;
|
|
|
|
id = tegra_get_cpu_powergate_id(cpuid);
|
|
if (id < 0)
|
|
return false;
|
|
|
|
return tegra_powergate_is_powered(id);
|
|
}
|
|
|
|
/**
|
|
* tegra_pmc_cpu_power_on() - power on CPU partition
|
|
* @cpuid: CPU partition ID
|
|
*/
|
|
int tegra_pmc_cpu_power_on(unsigned int cpuid)
|
|
{
|
|
int id;
|
|
|
|
id = tegra_get_cpu_powergate_id(cpuid);
|
|
if (id < 0)
|
|
return id;
|
|
|
|
return tegra_powergate_set(id, true);
|
|
}
|
|
|
|
/**
|
|
* tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
|
|
* @cpuid: CPU partition ID
|
|
*/
|
|
int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
|
|
{
|
|
int id;
|
|
|
|
id = tegra_get_cpu_powergate_id(cpuid);
|
|
if (id < 0)
|
|
return id;
|
|
|
|
return tegra_powergate_remove_clamping(id);
|
|
}
|
|
#endif /* CONFIG_SMP */
|
|
|
|
static int tegra_pmc_restart_notify(struct notifier_block *this,
|
|
unsigned long action, void *data)
|
|
{
|
|
const char *cmd = data;
|
|
u32 value;
|
|
|
|
value = readl(pmc->scratch + pmc->soc->regs->scratch0);
|
|
value &= ~PMC_SCRATCH0_MODE_MASK;
|
|
|
|
if (cmd) {
|
|
if (strcmp(cmd, "recovery") == 0)
|
|
value |= PMC_SCRATCH0_MODE_RECOVERY;
|
|
|
|
if (strcmp(cmd, "bootloader") == 0)
|
|
value |= PMC_SCRATCH0_MODE_BOOTLOADER;
|
|
|
|
if (strcmp(cmd, "forced-recovery") == 0)
|
|
value |= PMC_SCRATCH0_MODE_RCM;
|
|
}
|
|
|
|
writel(value, pmc->scratch + pmc->soc->regs->scratch0);
|
|
|
|
/* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
|
|
value = tegra_pmc_readl(PMC_CNTRL);
|
|
value |= PMC_CNTRL_MAIN_RST;
|
|
tegra_pmc_writel(value, PMC_CNTRL);
|
|
|
|
return NOTIFY_DONE;
|
|
}
|
|
|
|
static struct notifier_block tegra_pmc_restart_handler = {
|
|
.notifier_call = tegra_pmc_restart_notify,
|
|
.priority = 128,
|
|
};
|
|
|
|
static int powergate_show(struct seq_file *s, void *data)
|
|
{
|
|
unsigned int i;
|
|
int status;
|
|
|
|
seq_printf(s, " powergate powered\n");
|
|
seq_printf(s, "------------------\n");
|
|
|
|
for (i = 0; i < pmc->soc->num_powergates; i++) {
|
|
status = tegra_powergate_is_powered(i);
|
|
if (status < 0)
|
|
continue;
|
|
|
|
seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
|
|
status ? "yes" : "no");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int powergate_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, powergate_show, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations powergate_fops = {
|
|
.open = powergate_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
static int tegra_powergate_debugfs_init(void)
|
|
{
|
|
pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
|
|
&powergate_fops);
|
|
if (!pmc->debugfs)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
|
|
struct device_node *np)
|
|
{
|
|
struct clk *clk;
|
|
unsigned int i, count;
|
|
int err;
|
|
|
|
count = of_clk_get_parent_count(np);
|
|
if (count == 0)
|
|
return -ENODEV;
|
|
|
|
pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
|
|
if (!pg->clks)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
pg->clks[i] = of_clk_get(np, i);
|
|
if (IS_ERR(pg->clks[i])) {
|
|
err = PTR_ERR(pg->clks[i]);
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
pg->num_clks = count;
|
|
|
|
return 0;
|
|
|
|
err:
|
|
while (i--)
|
|
clk_put(pg->clks[i]);
|
|
|
|
kfree(pg->clks);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
|
|
struct device_node *np, bool off)
|
|
{
|
|
int err;
|
|
|
|
pg->reset = of_reset_control_array_get_exclusive(np);
|
|
if (IS_ERR(pg->reset)) {
|
|
err = PTR_ERR(pg->reset);
|
|
pr_err("failed to get device resets: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
if (off)
|
|
err = reset_control_assert(pg->reset);
|
|
else
|
|
err = reset_control_deassert(pg->reset);
|
|
|
|
if (err)
|
|
reset_control_put(pg->reset);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
|
|
{
|
|
struct tegra_powergate *pg;
|
|
int id, err;
|
|
bool off;
|
|
|
|
pg = kzalloc(sizeof(*pg), GFP_KERNEL);
|
|
if (!pg)
|
|
return;
|
|
|
|
id = tegra_powergate_lookup(pmc, np->name);
|
|
if (id < 0) {
|
|
pr_err("powergate lookup failed for %s: %d\n", np->name, id);
|
|
goto free_mem;
|
|
}
|
|
|
|
/*
|
|
* Clear the bit for this powergate so it cannot be managed
|
|
* directly via the legacy APIs for controlling powergates.
|
|
*/
|
|
clear_bit(id, pmc->powergates_available);
|
|
|
|
pg->id = id;
|
|
pg->genpd.name = np->name;
|
|
pg->genpd.power_off = tegra_genpd_power_off;
|
|
pg->genpd.power_on = tegra_genpd_power_on;
|
|
pg->pmc = pmc;
|
|
|
|
off = !tegra_powergate_is_powered(pg->id);
|
|
|
|
err = tegra_powergate_of_get_clks(pg, np);
|
|
if (err < 0) {
|
|
pr_err("failed to get clocks for %s: %d\n", np->name, err);
|
|
goto set_available;
|
|
}
|
|
|
|
err = tegra_powergate_of_get_resets(pg, np, off);
|
|
if (err < 0) {
|
|
pr_err("failed to get resets for %s: %d\n", np->name, err);
|
|
goto remove_clks;
|
|
}
|
|
|
|
if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
|
|
if (off)
|
|
WARN_ON(tegra_powergate_power_up(pg, true));
|
|
|
|
goto remove_resets;
|
|
}
|
|
|
|
/*
|
|
* FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
|
|
* host and super-speed partitions. Once the XHCI driver
|
|
* manages the partitions itself this code can be removed. Note
|
|
* that we don't register these partitions with the genpd core
|
|
* to avoid it from powering down the partitions as they appear
|
|
* to be unused.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
|
|
(id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
|
|
if (off)
|
|
WARN_ON(tegra_powergate_power_up(pg, true));
|
|
|
|
goto remove_resets;
|
|
}
|
|
|
|
err = pm_genpd_init(&pg->genpd, NULL, off);
|
|
if (err < 0) {
|
|
pr_err("failed to initialise PM domain %s: %d\n", np->name,
|
|
err);
|
|
goto remove_resets;
|
|
}
|
|
|
|
err = of_genpd_add_provider_simple(np, &pg->genpd);
|
|
if (err < 0) {
|
|
pr_err("failed to add PM domain provider for %s: %d\n",
|
|
np->name, err);
|
|
goto remove_genpd;
|
|
}
|
|
|
|
pr_debug("added PM domain %s\n", pg->genpd.name);
|
|
|
|
return;
|
|
|
|
remove_genpd:
|
|
pm_genpd_remove(&pg->genpd);
|
|
|
|
remove_resets:
|
|
reset_control_put(pg->reset);
|
|
|
|
remove_clks:
|
|
while (pg->num_clks--)
|
|
clk_put(pg->clks[pg->num_clks]);
|
|
|
|
kfree(pg->clks);
|
|
|
|
set_available:
|
|
set_bit(id, pmc->powergates_available);
|
|
|
|
free_mem:
|
|
kfree(pg);
|
|
}
|
|
|
|
static void tegra_powergate_init(struct tegra_pmc *pmc,
|
|
struct device_node *parent)
|
|
{
|
|
struct device_node *np, *child;
|
|
unsigned int i;
|
|
|
|
/* Create a bitmap of the available and valid partitions */
|
|
for (i = 0; i < pmc->soc->num_powergates; i++)
|
|
if (pmc->soc->powergates[i])
|
|
set_bit(i, pmc->powergates_available);
|
|
|
|
np = of_get_child_by_name(parent, "powergates");
|
|
if (!np)
|
|
return;
|
|
|
|
for_each_child_of_node(np, child)
|
|
tegra_powergate_add(pmc, child);
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
static const struct tegra_io_pad_soc *
|
|
tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < pmc->soc->num_io_pads; i++)
|
|
if (pmc->soc->io_pads[i].id == id)
|
|
return &pmc->soc->io_pads[i];
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
|
|
unsigned long *status, u32 *mask)
|
|
{
|
|
const struct tegra_io_pad_soc *pad;
|
|
unsigned long rate, value;
|
|
|
|
pad = tegra_io_pad_find(pmc, id);
|
|
if (!pad) {
|
|
pr_err("invalid I/O pad ID %u\n", id);
|
|
return -ENOENT;
|
|
}
|
|
|
|
if (pad->dpd == UINT_MAX)
|
|
return -ENOTSUPP;
|
|
|
|
*mask = BIT(pad->dpd % 32);
|
|
|
|
if (pad->dpd < 32) {
|
|
*status = pmc->soc->regs->dpd_status;
|
|
*request = pmc->soc->regs->dpd_req;
|
|
} else {
|
|
*status = pmc->soc->regs->dpd2_status;
|
|
*request = pmc->soc->regs->dpd2_req;
|
|
}
|
|
|
|
if (pmc->clk) {
|
|
rate = clk_get_rate(pmc->clk);
|
|
if (!rate) {
|
|
pr_err("failed to get clock rate\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
|
|
|
|
/* must be at least 200 ns, in APB (PCLK) clock cycles */
|
|
value = DIV_ROUND_UP(1000000000, rate);
|
|
value = DIV_ROUND_UP(200, value);
|
|
tegra_pmc_writel(value, SEL_DPD_TIM);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_io_pad_poll(unsigned long offset, u32 mask,
|
|
u32 val, unsigned long timeout)
|
|
{
|
|
u32 value;
|
|
|
|
timeout = jiffies + msecs_to_jiffies(timeout);
|
|
|
|
while (time_after(timeout, jiffies)) {
|
|
value = tegra_pmc_readl(offset);
|
|
if ((value & mask) == val)
|
|
return 0;
|
|
|
|
usleep_range(250, 1000);
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
static void tegra_io_pad_unprepare(void)
|
|
{
|
|
if (pmc->clk)
|
|
tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
|
|
}
|
|
|
|
/**
|
|
* tegra_io_pad_power_enable() - enable power to I/O pad
|
|
* @id: Tegra I/O pad ID for which to enable power
|
|
*
|
|
* Returns: 0 on success or a negative error code on failure.
|
|
*/
|
|
int tegra_io_pad_power_enable(enum tegra_io_pad id)
|
|
{
|
|
unsigned long request, status;
|
|
u32 mask;
|
|
int err;
|
|
|
|
mutex_lock(&pmc->powergates_lock);
|
|
|
|
err = tegra_io_pad_prepare(id, &request, &status, &mask);
|
|
if (err < 0) {
|
|
pr_err("failed to prepare I/O pad: %d\n", err);
|
|
goto unlock;
|
|
}
|
|
|
|
tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
|
|
|
|
err = tegra_io_pad_poll(status, mask, 0, 250);
|
|
if (err < 0) {
|
|
pr_err("failed to enable I/O pad: %d\n", err);
|
|
goto unlock;
|
|
}
|
|
|
|
tegra_io_pad_unprepare();
|
|
|
|
unlock:
|
|
mutex_unlock(&pmc->powergates_lock);
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(tegra_io_pad_power_enable);
|
|
|
|
/**
|
|
* tegra_io_pad_power_disable() - disable power to I/O pad
|
|
* @id: Tegra I/O pad ID for which to disable power
|
|
*
|
|
* Returns: 0 on success or a negative error code on failure.
|
|
*/
|
|
int tegra_io_pad_power_disable(enum tegra_io_pad id)
|
|
{
|
|
unsigned long request, status;
|
|
u32 mask;
|
|
int err;
|
|
|
|
mutex_lock(&pmc->powergates_lock);
|
|
|
|
err = tegra_io_pad_prepare(id, &request, &status, &mask);
|
|
if (err < 0) {
|
|
pr_err("failed to prepare I/O pad: %d\n", err);
|
|
goto unlock;
|
|
}
|
|
|
|
tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
|
|
|
|
err = tegra_io_pad_poll(status, mask, mask, 250);
|
|
if (err < 0) {
|
|
pr_err("failed to disable I/O pad: %d\n", err);
|
|
goto unlock;
|
|
}
|
|
|
|
tegra_io_pad_unprepare();
|
|
|
|
unlock:
|
|
mutex_unlock(&pmc->powergates_lock);
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(tegra_io_pad_power_disable);
|
|
|
|
int tegra_io_pad_set_voltage(enum tegra_io_pad id,
|
|
enum tegra_io_pad_voltage voltage)
|
|
{
|
|
const struct tegra_io_pad_soc *pad;
|
|
u32 value;
|
|
|
|
pad = tegra_io_pad_find(pmc, id);
|
|
if (!pad)
|
|
return -ENOENT;
|
|
|
|
if (pad->voltage == UINT_MAX)
|
|
return -ENOTSUPP;
|
|
|
|
mutex_lock(&pmc->powergates_lock);
|
|
|
|
/* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
|
|
value = tegra_pmc_readl(PMC_PWR_DET);
|
|
value |= BIT(pad->voltage);
|
|
tegra_pmc_writel(value, PMC_PWR_DET);
|
|
|
|
/* update I/O voltage */
|
|
value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
|
|
|
|
if (voltage == TEGRA_IO_PAD_1800000UV)
|
|
value &= ~BIT(pad->voltage);
|
|
else
|
|
value |= BIT(pad->voltage);
|
|
|
|
tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
|
|
|
|
mutex_unlock(&pmc->powergates_lock);
|
|
|
|
usleep_range(100, 250);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(tegra_io_pad_set_voltage);
|
|
|
|
int tegra_io_pad_get_voltage(enum tegra_io_pad id)
|
|
{
|
|
const struct tegra_io_pad_soc *pad;
|
|
u32 value;
|
|
|
|
pad = tegra_io_pad_find(pmc, id);
|
|
if (!pad)
|
|
return -ENOENT;
|
|
|
|
if (pad->voltage == UINT_MAX)
|
|
return -ENOTSUPP;
|
|
|
|
value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
|
|
|
|
if ((value & BIT(pad->voltage)) == 0)
|
|
return TEGRA_IO_PAD_1800000UV;
|
|
|
|
return TEGRA_IO_PAD_3300000UV;
|
|
}
|
|
EXPORT_SYMBOL(tegra_io_pad_get_voltage);
|
|
|
|
/**
|
|
* tegra_io_rail_power_on() - enable power to I/O rail
|
|
* @id: Tegra I/O pad ID for which to enable power
|
|
*
|
|
* See also: tegra_io_pad_power_enable()
|
|
*/
|
|
int tegra_io_rail_power_on(unsigned int id)
|
|
{
|
|
return tegra_io_pad_power_enable(id);
|
|
}
|
|
EXPORT_SYMBOL(tegra_io_rail_power_on);
|
|
|
|
/**
|
|
* tegra_io_rail_power_off() - disable power to I/O rail
|
|
* @id: Tegra I/O pad ID for which to disable power
|
|
*
|
|
* See also: tegra_io_pad_power_disable()
|
|
*/
|
|
int tegra_io_rail_power_off(unsigned int id)
|
|
{
|
|
return tegra_io_pad_power_disable(id);
|
|
}
|
|
EXPORT_SYMBOL(tegra_io_rail_power_off);
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
|
|
{
|
|
return pmc->suspend_mode;
|
|
}
|
|
|
|
void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
|
|
{
|
|
if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
|
|
return;
|
|
|
|
pmc->suspend_mode = mode;
|
|
}
|
|
|
|
void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
|
|
{
|
|
unsigned long long rate = 0;
|
|
u32 value;
|
|
|
|
switch (mode) {
|
|
case TEGRA_SUSPEND_LP1:
|
|
rate = 32768;
|
|
break;
|
|
|
|
case TEGRA_SUSPEND_LP2:
|
|
rate = clk_get_rate(pmc->clk);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (WARN_ON_ONCE(rate == 0))
|
|
rate = 100000000;
|
|
|
|
if (rate != pmc->rate) {
|
|
u64 ticks;
|
|
|
|
ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
|
|
do_div(ticks, USEC_PER_SEC);
|
|
tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
|
|
|
|
ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
|
|
do_div(ticks, USEC_PER_SEC);
|
|
tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
|
|
|
|
wmb();
|
|
|
|
pmc->rate = rate;
|
|
}
|
|
|
|
value = tegra_pmc_readl(PMC_CNTRL);
|
|
value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
|
|
value |= PMC_CNTRL_CPU_PWRREQ_OE;
|
|
tegra_pmc_writel(value, PMC_CNTRL);
|
|
}
|
|
#endif
|
|
|
|
static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
|
|
{
|
|
u32 value, values[2];
|
|
|
|
if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
|
|
} else {
|
|
switch (value) {
|
|
case 0:
|
|
pmc->suspend_mode = TEGRA_SUSPEND_LP0;
|
|
break;
|
|
|
|
case 1:
|
|
pmc->suspend_mode = TEGRA_SUSPEND_LP1;
|
|
break;
|
|
|
|
case 2:
|
|
pmc->suspend_mode = TEGRA_SUSPEND_LP2;
|
|
break;
|
|
|
|
default:
|
|
pmc->suspend_mode = TEGRA_SUSPEND_NONE;
|
|
break;
|
|
}
|
|
}
|
|
|
|
pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
|
|
|
|
if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
|
|
pmc->suspend_mode = TEGRA_SUSPEND_NONE;
|
|
|
|
pmc->cpu_good_time = value;
|
|
|
|
if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
|
|
pmc->suspend_mode = TEGRA_SUSPEND_NONE;
|
|
|
|
pmc->cpu_off_time = value;
|
|
|
|
if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
|
|
values, ARRAY_SIZE(values)))
|
|
pmc->suspend_mode = TEGRA_SUSPEND_NONE;
|
|
|
|
pmc->core_osc_time = values[0];
|
|
pmc->core_pmu_time = values[1];
|
|
|
|
if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
|
|
pmc->suspend_mode = TEGRA_SUSPEND_NONE;
|
|
|
|
pmc->core_off_time = value;
|
|
|
|
pmc->corereq_high = of_property_read_bool(np,
|
|
"nvidia,core-power-req-active-high");
|
|
|
|
pmc->sysclkreq_high = of_property_read_bool(np,
|
|
"nvidia,sys-clock-req-active-high");
|
|
|
|
pmc->combined_req = of_property_read_bool(np,
|
|
"nvidia,combined-power-req");
|
|
|
|
pmc->cpu_pwr_good_en = of_property_read_bool(np,
|
|
"nvidia,cpu-pwr-good-en");
|
|
|
|
if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
|
|
ARRAY_SIZE(values)))
|
|
if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
|
|
pmc->suspend_mode = TEGRA_SUSPEND_LP1;
|
|
|
|
pmc->lp0_vec_phys = values[0];
|
|
pmc->lp0_vec_size = values[1];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_pmc_init(struct tegra_pmc *pmc)
|
|
{
|
|
if (pmc->soc->init)
|
|
pmc->soc->init(pmc);
|
|
}
|
|
|
|
static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
|
|
{
|
|
static const char disabled[] = "emergency thermal reset disabled";
|
|
u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
|
|
struct device *dev = pmc->dev;
|
|
struct device_node *np;
|
|
u32 value, checksum;
|
|
|
|
if (!pmc->soc->has_tsense_reset)
|
|
return;
|
|
|
|
np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
|
|
if (!np) {
|
|
dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
|
|
return;
|
|
}
|
|
|
|
if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
|
|
dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
|
|
goto out;
|
|
}
|
|
|
|
if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
|
|
dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
|
|
goto out;
|
|
}
|
|
|
|
if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
|
|
dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
|
|
goto out;
|
|
}
|
|
|
|
if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
|
|
dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
|
|
goto out;
|
|
}
|
|
|
|
if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
|
|
pinmux = 0;
|
|
|
|
value = tegra_pmc_readl(PMC_SENSOR_CTRL);
|
|
value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
|
|
tegra_pmc_writel(value, PMC_SENSOR_CTRL);
|
|
|
|
value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
|
|
(reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
|
|
tegra_pmc_writel(value, PMC_SCRATCH54);
|
|
|
|
value = PMC_SCRATCH55_RESET_TEGRA;
|
|
value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
|
|
value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
|
|
value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
|
|
|
|
/*
|
|
* Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
|
|
* contain the checksum and are currently zero, so they are not added.
|
|
*/
|
|
checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
|
|
+ ((value >> 24) & 0xff);
|
|
checksum &= 0xff;
|
|
checksum = 0x100 - checksum;
|
|
|
|
value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
|
|
|
|
tegra_pmc_writel(value, PMC_SCRATCH55);
|
|
|
|
value = tegra_pmc_readl(PMC_SENSOR_CTRL);
|
|
value |= PMC_SENSOR_CTRL_ENABLE_RST;
|
|
tegra_pmc_writel(value, PMC_SENSOR_CTRL);
|
|
|
|
dev_info(pmc->dev, "emergency thermal reset enabled\n");
|
|
|
|
out:
|
|
of_node_put(np);
|
|
}
|
|
|
|
static int tegra_pmc_probe(struct platform_device *pdev)
|
|
{
|
|
void __iomem *base;
|
|
struct resource *res;
|
|
int err;
|
|
|
|
/*
|
|
* Early initialisation should have configured an initial
|
|
* register mapping and setup the soc data pointer. If these
|
|
* are not valid then something went badly wrong!
|
|
*/
|
|
if (WARN_ON(!pmc->base || !pmc->soc))
|
|
return -ENODEV;
|
|
|
|
err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* take over the memory region from the early initialization */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
|
|
if (res) {
|
|
pmc->wake = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(pmc->wake))
|
|
return PTR_ERR(pmc->wake);
|
|
} else {
|
|
pmc->wake = base;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
|
|
if (res) {
|
|
pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(pmc->aotag))
|
|
return PTR_ERR(pmc->aotag);
|
|
} else {
|
|
pmc->aotag = base;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
|
|
if (res) {
|
|
pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(pmc->scratch))
|
|
return PTR_ERR(pmc->scratch);
|
|
} else {
|
|
pmc->scratch = base;
|
|
}
|
|
|
|
pmc->clk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(pmc->clk)) {
|
|
err = PTR_ERR(pmc->clk);
|
|
|
|
if (err != -ENOENT) {
|
|
dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
pmc->clk = NULL;
|
|
}
|
|
|
|
pmc->dev = &pdev->dev;
|
|
|
|
tegra_pmc_init(pmc);
|
|
|
|
tegra_pmc_init_tsense_reset(pmc);
|
|
|
|
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
|
|
err = tegra_powergate_debugfs_init();
|
|
if (err < 0)
|
|
return err;
|
|
}
|
|
|
|
err = register_restart_handler(&tegra_pmc_restart_handler);
|
|
if (err) {
|
|
debugfs_remove(pmc->debugfs);
|
|
dev_err(&pdev->dev, "unable to register restart handler, %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
mutex_lock(&pmc->powergates_lock);
|
|
iounmap(pmc->base);
|
|
pmc->base = base;
|
|
mutex_unlock(&pmc->powergates_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
|
|
static int tegra_pmc_suspend(struct device *dev)
|
|
{
|
|
tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_pmc_resume(struct device *dev)
|
|
{
|
|
tegra_pmc_writel(0x0, PMC_SCRATCH41);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
|
|
|
|
#endif
|
|
|
|
static const char * const tegra20_powergates[] = {
|
|
[TEGRA_POWERGATE_CPU] = "cpu",
|
|
[TEGRA_POWERGATE_3D] = "3d",
|
|
[TEGRA_POWERGATE_VENC] = "venc",
|
|
[TEGRA_POWERGATE_VDEC] = "vdec",
|
|
[TEGRA_POWERGATE_PCIE] = "pcie",
|
|
[TEGRA_POWERGATE_L2] = "l2",
|
|
[TEGRA_POWERGATE_MPE] = "mpe",
|
|
};
|
|
|
|
static const struct tegra_pmc_regs tegra20_pmc_regs = {
|
|
.scratch0 = 0x50,
|
|
.dpd_req = 0x1b8,
|
|
.dpd_status = 0x1bc,
|
|
.dpd2_req = 0x1c0,
|
|
.dpd2_status = 0x1c4,
|
|
};
|
|
|
|
static void tegra20_pmc_init(struct tegra_pmc *pmc)
|
|
{
|
|
u32 value;
|
|
|
|
/* Always enable CPU power request */
|
|
value = tegra_pmc_readl(PMC_CNTRL);
|
|
value |= PMC_CNTRL_CPU_PWRREQ_OE;
|
|
tegra_pmc_writel(value, PMC_CNTRL);
|
|
|
|
value = tegra_pmc_readl(PMC_CNTRL);
|
|
|
|
if (pmc->sysclkreq_high)
|
|
value &= ~PMC_CNTRL_SYSCLK_POLARITY;
|
|
else
|
|
value |= PMC_CNTRL_SYSCLK_POLARITY;
|
|
|
|
/* configure the output polarity while the request is tristated */
|
|
tegra_pmc_writel(value, PMC_CNTRL);
|
|
|
|
/* now enable the request */
|
|
value = tegra_pmc_readl(PMC_CNTRL);
|
|
value |= PMC_CNTRL_SYSCLK_OE;
|
|
tegra_pmc_writel(value, PMC_CNTRL);
|
|
}
|
|
|
|
static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
|
|
struct device_node *np,
|
|
bool invert)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_pmc_readl(PMC_CNTRL);
|
|
|
|
if (invert)
|
|
value |= PMC_CNTRL_INTR_POLARITY;
|
|
else
|
|
value &= ~PMC_CNTRL_INTR_POLARITY;
|
|
|
|
tegra_pmc_writel(value, PMC_CNTRL);
|
|
}
|
|
|
|
static const struct tegra_pmc_soc tegra20_pmc_soc = {
|
|
.num_powergates = ARRAY_SIZE(tegra20_powergates),
|
|
.powergates = tegra20_powergates,
|
|
.num_cpu_powergates = 0,
|
|
.cpu_powergates = NULL,
|
|
.has_tsense_reset = false,
|
|
.has_gpu_clamps = false,
|
|
.num_io_pads = 0,
|
|
.io_pads = NULL,
|
|
.regs = &tegra20_pmc_regs,
|
|
.init = tegra20_pmc_init,
|
|
.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
|
|
};
|
|
|
|
static const char * const tegra30_powergates[] = {
|
|
[TEGRA_POWERGATE_CPU] = "cpu0",
|
|
[TEGRA_POWERGATE_3D] = "3d0",
|
|
[TEGRA_POWERGATE_VENC] = "venc",
|
|
[TEGRA_POWERGATE_VDEC] = "vdec",
|
|
[TEGRA_POWERGATE_PCIE] = "pcie",
|
|
[TEGRA_POWERGATE_L2] = "l2",
|
|
[TEGRA_POWERGATE_MPE] = "mpe",
|
|
[TEGRA_POWERGATE_HEG] = "heg",
|
|
[TEGRA_POWERGATE_SATA] = "sata",
|
|
[TEGRA_POWERGATE_CPU1] = "cpu1",
|
|
[TEGRA_POWERGATE_CPU2] = "cpu2",
|
|
[TEGRA_POWERGATE_CPU3] = "cpu3",
|
|
[TEGRA_POWERGATE_CELP] = "celp",
|
|
[TEGRA_POWERGATE_3D1] = "3d1",
|
|
};
|
|
|
|
static const u8 tegra30_cpu_powergates[] = {
|
|
TEGRA_POWERGATE_CPU,
|
|
TEGRA_POWERGATE_CPU1,
|
|
TEGRA_POWERGATE_CPU2,
|
|
TEGRA_POWERGATE_CPU3,
|
|
};
|
|
|
|
static const struct tegra_pmc_soc tegra30_pmc_soc = {
|
|
.num_powergates = ARRAY_SIZE(tegra30_powergates),
|
|
.powergates = tegra30_powergates,
|
|
.num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
|
|
.cpu_powergates = tegra30_cpu_powergates,
|
|
.has_tsense_reset = true,
|
|
.has_gpu_clamps = false,
|
|
.num_io_pads = 0,
|
|
.io_pads = NULL,
|
|
.regs = &tegra20_pmc_regs,
|
|
.init = tegra20_pmc_init,
|
|
.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
|
|
};
|
|
|
|
static const char * const tegra114_powergates[] = {
|
|
[TEGRA_POWERGATE_CPU] = "crail",
|
|
[TEGRA_POWERGATE_3D] = "3d",
|
|
[TEGRA_POWERGATE_VENC] = "venc",
|
|
[TEGRA_POWERGATE_VDEC] = "vdec",
|
|
[TEGRA_POWERGATE_MPE] = "mpe",
|
|
[TEGRA_POWERGATE_HEG] = "heg",
|
|
[TEGRA_POWERGATE_CPU1] = "cpu1",
|
|
[TEGRA_POWERGATE_CPU2] = "cpu2",
|
|
[TEGRA_POWERGATE_CPU3] = "cpu3",
|
|
[TEGRA_POWERGATE_CELP] = "celp",
|
|
[TEGRA_POWERGATE_CPU0] = "cpu0",
|
|
[TEGRA_POWERGATE_C0NC] = "c0nc",
|
|
[TEGRA_POWERGATE_C1NC] = "c1nc",
|
|
[TEGRA_POWERGATE_DIS] = "dis",
|
|
[TEGRA_POWERGATE_DISB] = "disb",
|
|
[TEGRA_POWERGATE_XUSBA] = "xusba",
|
|
[TEGRA_POWERGATE_XUSBB] = "xusbb",
|
|
[TEGRA_POWERGATE_XUSBC] = "xusbc",
|
|
};
|
|
|
|
static const u8 tegra114_cpu_powergates[] = {
|
|
TEGRA_POWERGATE_CPU0,
|
|
TEGRA_POWERGATE_CPU1,
|
|
TEGRA_POWERGATE_CPU2,
|
|
TEGRA_POWERGATE_CPU3,
|
|
};
|
|
|
|
static const struct tegra_pmc_soc tegra114_pmc_soc = {
|
|
.num_powergates = ARRAY_SIZE(tegra114_powergates),
|
|
.powergates = tegra114_powergates,
|
|
.num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
|
|
.cpu_powergates = tegra114_cpu_powergates,
|
|
.has_tsense_reset = true,
|
|
.has_gpu_clamps = false,
|
|
.num_io_pads = 0,
|
|
.io_pads = NULL,
|
|
.regs = &tegra20_pmc_regs,
|
|
.init = tegra20_pmc_init,
|
|
.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
|
|
};
|
|
|
|
static const char * const tegra124_powergates[] = {
|
|
[TEGRA_POWERGATE_CPU] = "crail",
|
|
[TEGRA_POWERGATE_3D] = "3d",
|
|
[TEGRA_POWERGATE_VENC] = "venc",
|
|
[TEGRA_POWERGATE_PCIE] = "pcie",
|
|
[TEGRA_POWERGATE_VDEC] = "vdec",
|
|
[TEGRA_POWERGATE_MPE] = "mpe",
|
|
[TEGRA_POWERGATE_HEG] = "heg",
|
|
[TEGRA_POWERGATE_SATA] = "sata",
|
|
[TEGRA_POWERGATE_CPU1] = "cpu1",
|
|
[TEGRA_POWERGATE_CPU2] = "cpu2",
|
|
[TEGRA_POWERGATE_CPU3] = "cpu3",
|
|
[TEGRA_POWERGATE_CELP] = "celp",
|
|
[TEGRA_POWERGATE_CPU0] = "cpu0",
|
|
[TEGRA_POWERGATE_C0NC] = "c0nc",
|
|
[TEGRA_POWERGATE_C1NC] = "c1nc",
|
|
[TEGRA_POWERGATE_SOR] = "sor",
|
|
[TEGRA_POWERGATE_DIS] = "dis",
|
|
[TEGRA_POWERGATE_DISB] = "disb",
|
|
[TEGRA_POWERGATE_XUSBA] = "xusba",
|
|
[TEGRA_POWERGATE_XUSBB] = "xusbb",
|
|
[TEGRA_POWERGATE_XUSBC] = "xusbc",
|
|
[TEGRA_POWERGATE_VIC] = "vic",
|
|
[TEGRA_POWERGATE_IRAM] = "iram",
|
|
};
|
|
|
|
static const u8 tegra124_cpu_powergates[] = {
|
|
TEGRA_POWERGATE_CPU0,
|
|
TEGRA_POWERGATE_CPU1,
|
|
TEGRA_POWERGATE_CPU2,
|
|
TEGRA_POWERGATE_CPU3,
|
|
};
|
|
|
|
static const struct tegra_io_pad_soc tegra124_io_pads[] = {
|
|
{ .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
|
|
};
|
|
|
|
static const struct tegra_pmc_soc tegra124_pmc_soc = {
|
|
.num_powergates = ARRAY_SIZE(tegra124_powergates),
|
|
.powergates = tegra124_powergates,
|
|
.num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
|
|
.cpu_powergates = tegra124_cpu_powergates,
|
|
.has_tsense_reset = true,
|
|
.has_gpu_clamps = true,
|
|
.num_io_pads = ARRAY_SIZE(tegra124_io_pads),
|
|
.io_pads = tegra124_io_pads,
|
|
.regs = &tegra20_pmc_regs,
|
|
.init = tegra20_pmc_init,
|
|
.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
|
|
};
|
|
|
|
static const char * const tegra210_powergates[] = {
|
|
[TEGRA_POWERGATE_CPU] = "crail",
|
|
[TEGRA_POWERGATE_3D] = "3d",
|
|
[TEGRA_POWERGATE_VENC] = "venc",
|
|
[TEGRA_POWERGATE_PCIE] = "pcie",
|
|
[TEGRA_POWERGATE_MPE] = "mpe",
|
|
[TEGRA_POWERGATE_SATA] = "sata",
|
|
[TEGRA_POWERGATE_CPU1] = "cpu1",
|
|
[TEGRA_POWERGATE_CPU2] = "cpu2",
|
|
[TEGRA_POWERGATE_CPU3] = "cpu3",
|
|
[TEGRA_POWERGATE_CPU0] = "cpu0",
|
|
[TEGRA_POWERGATE_C0NC] = "c0nc",
|
|
[TEGRA_POWERGATE_SOR] = "sor",
|
|
[TEGRA_POWERGATE_DIS] = "dis",
|
|
[TEGRA_POWERGATE_DISB] = "disb",
|
|
[TEGRA_POWERGATE_XUSBA] = "xusba",
|
|
[TEGRA_POWERGATE_XUSBB] = "xusbb",
|
|
[TEGRA_POWERGATE_XUSBC] = "xusbc",
|
|
[TEGRA_POWERGATE_VIC] = "vic",
|
|
[TEGRA_POWERGATE_IRAM] = "iram",
|
|
[TEGRA_POWERGATE_NVDEC] = "nvdec",
|
|
[TEGRA_POWERGATE_NVJPG] = "nvjpg",
|
|
[TEGRA_POWERGATE_AUD] = "aud",
|
|
[TEGRA_POWERGATE_DFD] = "dfd",
|
|
[TEGRA_POWERGATE_VE2] = "ve2",
|
|
};
|
|
|
|
static const u8 tegra210_cpu_powergates[] = {
|
|
TEGRA_POWERGATE_CPU0,
|
|
TEGRA_POWERGATE_CPU1,
|
|
TEGRA_POWERGATE_CPU2,
|
|
TEGRA_POWERGATE_CPU3,
|
|
};
|
|
|
|
static const struct tegra_io_pad_soc tegra210_io_pads[] = {
|
|
{ .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
|
|
{ .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
|
|
{ .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
|
|
{ .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
|
|
{ .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
|
|
{ .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
|
|
{ .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
|
|
{ .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
|
|
{ .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
|
|
{ .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
|
|
{ .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
|
|
{ .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
|
|
{ .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
|
|
};
|
|
|
|
static const struct tegra_pmc_soc tegra210_pmc_soc = {
|
|
.num_powergates = ARRAY_SIZE(tegra210_powergates),
|
|
.powergates = tegra210_powergates,
|
|
.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
|
|
.cpu_powergates = tegra210_cpu_powergates,
|
|
.has_tsense_reset = true,
|
|
.has_gpu_clamps = true,
|
|
.needs_mbist_war = true,
|
|
.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
|
|
.io_pads = tegra210_io_pads,
|
|
.regs = &tegra20_pmc_regs,
|
|
.init = tegra20_pmc_init,
|
|
.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
|
|
};
|
|
|
|
static const struct tegra_io_pad_soc tegra186_io_pads[] = {
|
|
{ .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
|
|
{ .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
|
|
};
|
|
|
|
static const struct tegra_pmc_regs tegra186_pmc_regs = {
|
|
.scratch0 = 0x2000,
|
|
.dpd_req = 0x74,
|
|
.dpd_status = 0x78,
|
|
.dpd2_req = 0x7c,
|
|
.dpd2_status = 0x80,
|
|
};
|
|
|
|
static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
|
|
struct device_node *np,
|
|
bool invert)
|
|
{
|
|
struct resource regs;
|
|
void __iomem *wake;
|
|
u32 value;
|
|
int index;
|
|
|
|
index = of_property_match_string(np, "reg-names", "wake");
|
|
if (index < 0) {
|
|
pr_err("failed to find PMC wake registers\n");
|
|
return;
|
|
}
|
|
|
|
of_address_to_resource(np, index, ®s);
|
|
|
|
wake = ioremap_nocache(regs.start, resource_size(®s));
|
|
if (!wake) {
|
|
pr_err("failed to map PMC wake registers\n");
|
|
return;
|
|
}
|
|
|
|
value = readl(wake + WAKE_AOWAKE_CTRL);
|
|
|
|
if (invert)
|
|
value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
|
|
else
|
|
value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
|
|
|
|
writel(value, wake + WAKE_AOWAKE_CTRL);
|
|
|
|
iounmap(wake);
|
|
}
|
|
|
|
static const struct tegra_pmc_soc tegra186_pmc_soc = {
|
|
.num_powergates = 0,
|
|
.powergates = NULL,
|
|
.num_cpu_powergates = 0,
|
|
.cpu_powergates = NULL,
|
|
.has_tsense_reset = false,
|
|
.has_gpu_clamps = false,
|
|
.num_io_pads = ARRAY_SIZE(tegra186_io_pads),
|
|
.io_pads = tegra186_io_pads,
|
|
.regs = &tegra186_pmc_regs,
|
|
.init = NULL,
|
|
.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
|
|
};
|
|
|
|
static const struct of_device_id tegra_pmc_match[] = {
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{ .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc },
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{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
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{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
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{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
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{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
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{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
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{ .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
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{ .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
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{ }
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};
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static struct platform_driver tegra_pmc_driver = {
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.driver = {
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.name = "tegra-pmc",
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.suppress_bind_attrs = true,
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.of_match_table = tegra_pmc_match,
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#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
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.pm = &tegra_pmc_pm_ops,
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#endif
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},
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.probe = tegra_pmc_probe,
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};
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builtin_platform_driver(tegra_pmc_driver);
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/*
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* Early initialization to allow access to registers in the very early boot
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* process.
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*/
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static int __init tegra_pmc_early_init(void)
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{
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const struct of_device_id *match;
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struct device_node *np;
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struct resource regs;
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bool invert;
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mutex_init(&pmc->powergates_lock);
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np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
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if (!np) {
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/*
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* Fall back to legacy initialization for 32-bit ARM only. All
|
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* 64-bit ARM device tree files for Tegra are required to have
|
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* a PMC node.
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*
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* This is for backwards-compatibility with old device trees
|
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* that didn't contain a PMC node. Note that in this case the
|
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* SoC data can't be matched and therefore powergating is
|
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* disabled.
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*/
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if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
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pr_warn("DT node not found, powergating disabled\n");
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|
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|
regs.start = 0x7000e400;
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regs.end = 0x7000e7ff;
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regs.flags = IORESOURCE_MEM;
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|
|
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pr_warn("Using memory region %pR\n", ®s);
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} else {
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|
/*
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|
* At this point we're not running on Tegra, so play
|
|
* nice with multi-platform kernels.
|
|
*/
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return 0;
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|
}
|
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} else {
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/*
|
|
* Extract information from the device tree if we've found a
|
|
* matching node.
|
|
*/
|
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if (of_address_to_resource(np, 0, ®s) < 0) {
|
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pr_err("failed to get PMC registers\n");
|
|
of_node_put(np);
|
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return -ENXIO;
|
|
}
|
|
}
|
|
|
|
pmc->base = ioremap_nocache(regs.start, resource_size(®s));
|
|
if (!pmc->base) {
|
|
pr_err("failed to map PMC registers\n");
|
|
of_node_put(np);
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (np) {
|
|
pmc->soc = match->data;
|
|
|
|
tegra_powergate_init(pmc, np);
|
|
|
|
/*
|
|
* Invert the interrupt polarity if a PMC device tree node
|
|
* exists and contains the nvidia,invert-interrupt property.
|
|
*/
|
|
invert = of_property_read_bool(np, "nvidia,invert-interrupt");
|
|
|
|
pmc->soc->setup_irq_polarity(pmc, np, invert);
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(tegra_pmc_early_init);
|