171 lines
4.7 KiB
C
171 lines
4.7 KiB
C
/*
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* Copyright (C) 2001-2006 Storlink, Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/global_reg.h>
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#include <asm/mach/time.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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/*
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* Register definitions for the timers
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*/
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#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00)
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#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04)
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#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08)
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#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C)
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#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30)
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#define TIMER_1_CR_ENABLE (1 << 0)
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#define TIMER_1_CR_CLOCK (1 << 1)
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#define TIMER_1_CR_INT (1 << 2)
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#define TIMER_2_CR_ENABLE (1 << 3)
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#define TIMER_2_CR_CLOCK (1 << 4)
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#define TIMER_2_CR_INT (1 << 5)
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#define TIMER_3_CR_ENABLE (1 << 6)
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#define TIMER_3_CR_CLOCK (1 << 7)
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#define TIMER_3_CR_INT (1 << 8)
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static unsigned int tick_rate;
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static int gemini_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 cr;
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cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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/* This may be overdoing it, feel free to test without this */
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cr &= ~TIMER_2_CR_ENABLE;
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cr &= ~TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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/* Set next event */
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writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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cr |= TIMER_2_CR_ENABLE;
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cr |= TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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return 0;
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}
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static void gemini_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
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u32 cr;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* Start the timer */
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writel(period,
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TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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writel(period,
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TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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cr |= TIMER_2_CR_ENABLE;
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cr |= TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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/*
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* Disable also for oneshot: the set_next() call will
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* arm the timer instead.
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*/
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cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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cr &= ~TIMER_2_CR_ENABLE;
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cr &= ~TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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break;
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default:
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break;
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}
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}
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/* Use TIMER2 as clock event */
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static struct clock_event_device gemini_clockevent = {
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.name = "TIMER2",
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.rating = 300, /* Reasonably fast and accurate clock event */
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = gemini_timer_set_next_event,
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.set_mode = gemini_timer_set_mode,
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};
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &gemini_clockevent;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction gemini_timer_irq = {
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.name = "Gemini Timer Tick",
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.flags = IRQF_TIMER,
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.handler = gemini_timer_interrupt,
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};
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/*
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* Set up timer interrupt, and return the current time in seconds.
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*/
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void __init gemini_timer_init(void)
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{
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u32 reg_v;
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reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS));
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tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000;
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printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000);
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tick_rate /= 6; /* APB bus run AHB*(1/6) */
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switch(reg_v & CPU_AHB_RATIO_MASK) {
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case CPU_AHB_1_1:
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printk(KERN_CONT "(1/1)\n");
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break;
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case CPU_AHB_3_2:
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printk(KERN_CONT "(3/2)\n");
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break;
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case CPU_AHB_24_13:
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printk(KERN_CONT "(24/13)\n");
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break;
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case CPU_AHB_2_1:
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printk(KERN_CONT "(2/1)\n");
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break;
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}
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/*
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* Make irqs happen for the system timer
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*/
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setup_irq(IRQ_TIMER2, &gemini_timer_irq);
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/* Enable and use TIMER1 as clock source */
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writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)));
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writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE)));
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writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)),
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"TIMER1", tick_rate, 300, 32,
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clocksource_mmio_readl_up))
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pr_err("timer: failed to initialize gemini clock source\n");
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/* Configure and register the clockevent */
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clockevents_config_and_register(&gemini_clockevent, tick_rate,
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1, 0xffffffff);
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}
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