100 lines
1.8 KiB
ArmAsm
100 lines
1.8 KiB
ArmAsm
#include <asm/thread_info.h>
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#include <asm/trap_block.h>
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#include <asm/spitfire.h>
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#include <asm/ptrace.h>
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#include <asm/head.h>
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.text
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.align 8
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.globl user_rtt_fill_fixup_common
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user_rtt_fill_fixup_common:
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rdpr %cwp, %g1
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add %g1, 1, %g1
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wrpr %g1, 0x0, %cwp
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rdpr %wstate, %g2
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sll %g2, 3, %g2
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wrpr %g2, 0x0, %wstate
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/* We know %canrestore and %otherwin are both zero. */
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sethi %hi(sparc64_kern_pri_context), %g2
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ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
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mov PRIMARY_CONTEXT, %g1
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661: stxa %g2, [%g1] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %g2, [%g1] ASI_MMU
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.previous
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sethi %hi(KERNBASE), %g1
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flush %g1
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mov %g4, %l4
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mov %g5, %l5
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brnz,pn %g3, 1f
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mov %g3, %l3
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or %g4, FAULT_CODE_WINFIXUP, %g4
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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1:
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mov %g6, %l1
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wrpr %g0, 0x0, %tl
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661: nop
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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SET_GL(0)
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.previous
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wrpr %g0, RTRAP_PSTATE, %pstate
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mov %l1, %g6
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ldx [%g6 + TI_TASK], %g4
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LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
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brnz,pn %l3, 1f
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nop
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call do_sparc64_fault
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop
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1: cmp %g3, 2
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bne,pn %xcc, 2f
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nop
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sethi %hi(tlb_type), %g1
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lduw [%g1 + %lo(tlb_type)], %g1
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cmp %g1, 3
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bne,pt %icc, 1f
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add %sp, PTREGS_OFF, %o0
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mov %l4, %o2
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call sun4v_do_mna
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mov %l5, %o1
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ba,a,pt %xcc, rtrap
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1: mov %l4, %o1
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mov %l5, %o2
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call mem_address_unaligned
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nop
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ba,a,pt %xcc, rtrap
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2: sethi %hi(tlb_type), %g1
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mov %l4, %o1
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lduw [%g1 + %lo(tlb_type)], %g1
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mov %l5, %o2
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cmp %g1, 3
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bne,pt %icc, 1f
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add %sp, PTREGS_OFF, %o0
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call sun4v_data_access_exception
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nop
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ba,a,pt %xcc, rtrap
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nop
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1: call spitfire_data_access_exception
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nop
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ba,a,pt %xcc, rtrap
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