119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi Ocelot IRQ controller driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/interrupt.h>
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#define ICPU_CFG_INTR_INTR_STICKY 0x10
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#define ICPU_CFG_INTR_INTR_ENA 0x18
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#define ICPU_CFG_INTR_INTR_ENA_CLR 0x1c
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#define ICPU_CFG_INTR_INTR_ENA_SET 0x20
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#define ICPU_CFG_INTR_DST_INTR_IDENT(x) (0x38 + 0x4 * (x))
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#define ICPU_CFG_INTR_INTR_TRIGGER(x) (0x5c + 0x4 * (x))
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#define OCELOT_NR_IRQ 24
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static void ocelot_irq_unmask(struct irq_data *data)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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struct irq_chip_type *ct = irq_data_get_chip_type(data);
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unsigned int mask = data->mask;
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u32 val;
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irq_gc_lock(gc);
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val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) |
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irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1));
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if (!(val & mask))
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irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY);
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*ct->mask_cache &= ~mask;
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irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET);
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irq_gc_unlock(gc);
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}
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static void ocelot_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_domain *d = irq_desc_get_handler_data(desc);
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
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u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0));
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chained_irq_enter(chip, desc);
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while (reg) {
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u32 hwirq = __fls(reg);
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generic_handle_irq(irq_find_mapping(d, hwirq));
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reg &= ~(BIT(hwirq));
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}
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chained_irq_exit(chip, desc);
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}
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static int __init ocelot_irq_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *domain;
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struct irq_chip_generic *gc;
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int parent_irq, ret;
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq)
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return -EINVAL;
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domain = irq_domain_add_linear(node, OCELOT_NR_IRQ,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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pr_err("%s: unable to add irq domain\n", node->name);
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return -ENOMEM;
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}
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ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1,
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"icpu", handle_level_irq,
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0, 0, 0);
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if (ret) {
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pr_err("%s: unable to alloc irq domain gc\n", node->name);
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goto err_domain_remove;
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}
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gc = irq_get_domain_generic_chip(domain, 0);
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gc->reg_base = of_iomap(node, 0);
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if (!gc->reg_base) {
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pr_err("%s: unable to map resource\n", node->name);
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ret = -ENOMEM;
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goto err_gc_free;
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}
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gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY;
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gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR;
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
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/* Mask and ack all interrupts */
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irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA);
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irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY);
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irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
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domain);
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return 0;
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err_gc_free:
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irq_free_generic_chip(gc);
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err_domain_remove:
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irq_domain_remove(domain);
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return ret;
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}
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IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
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