1099 lines
27 KiB
C
1099 lines
27 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/bitmap.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/mips-gic.h>
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#include <linux/of_address.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/mips-cm.h>
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#include <asm/setup.h>
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#include <asm/traps.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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unsigned int gic_present;
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struct gic_pcpu_mask {
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DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
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};
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struct gic_irq_spec {
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enum {
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GIC_DEVICE,
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GIC_IPI
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} type;
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union {
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struct cpumask *ipimask;
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unsigned int hwirq;
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};
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};
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static unsigned long __gic_base_addr;
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static void __iomem *gic_base;
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static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
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static DEFINE_SPINLOCK(gic_lock);
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static struct irq_domain *gic_irq_domain;
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static struct irq_domain *gic_dev_domain;
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static struct irq_domain *gic_ipi_domain;
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static int gic_shared_intrs;
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static int gic_vpes;
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static unsigned int gic_cpu_pin;
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static unsigned int timer_cpu_pin;
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static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
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static void __gic_irq_dispatch(void);
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static inline u32 gic_read32(unsigned int reg)
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{
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return __raw_readl(gic_base + reg);
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}
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static inline u64 gic_read64(unsigned int reg)
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{
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return __raw_readq(gic_base + reg);
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}
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static inline unsigned long gic_read(unsigned int reg)
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{
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if (!mips_cm_is64)
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return gic_read32(reg);
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else
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return gic_read64(reg);
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}
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static inline void gic_write32(unsigned int reg, u32 val)
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{
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return __raw_writel(val, gic_base + reg);
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}
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static inline void gic_write64(unsigned int reg, u64 val)
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{
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return __raw_writeq(val, gic_base + reg);
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}
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static inline void gic_write(unsigned int reg, unsigned long val)
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{
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if (!mips_cm_is64)
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return gic_write32(reg, (u32)val);
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else
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return gic_write64(reg, (u64)val);
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}
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static inline void gic_update_bits(unsigned int reg, unsigned long mask,
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unsigned long val)
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{
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unsigned long regval;
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regval = gic_read(reg);
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regval &= ~mask;
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regval |= val;
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gic_write(reg, regval);
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}
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static inline void gic_reset_mask(unsigned int intr)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
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1ul << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_mask(unsigned int intr)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
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1ul << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
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GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
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(unsigned long)pol << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
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GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
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(unsigned long)trig << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
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1ul << GIC_INTR_BIT(intr),
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(unsigned long)dual << GIC_INTR_BIT(intr));
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}
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static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
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{
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gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
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GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
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}
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static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
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GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
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GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
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}
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#ifdef CONFIG_CLKSRC_MIPS_GIC
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cycle_t gic_read_count(void)
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{
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unsigned int hi, hi2, lo;
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if (mips_cm_is64)
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return (cycle_t)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER));
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do {
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hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
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hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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} while (hi2 != hi);
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return (((cycle_t) hi) << 32) + lo;
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}
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unsigned int gic_get_count_width(void)
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{
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unsigned int bits, config;
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config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
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bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
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GIC_SH_CONFIG_COUNTBITS_SHF);
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return bits;
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}
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void gic_write_compare(cycle_t cnt)
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{
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if (mips_cm_is64) {
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt);
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} else {
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gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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}
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}
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void gic_write_cpu_compare(cycle_t cnt, int cpu)
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{
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unsigned long flags;
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local_irq_save(flags);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
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if (mips_cm_is64) {
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt);
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} else {
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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}
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local_irq_restore(flags);
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}
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cycle_t gic_read_compare(void)
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{
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unsigned int hi, lo;
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if (mips_cm_is64)
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return (cycle_t)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE));
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hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
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lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
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return (((cycle_t) hi) << 32) + lo;
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}
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void gic_start_count(void)
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{
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u32 gicconfig;
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/* Start the counter */
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gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
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gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
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gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
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}
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void gic_stop_count(void)
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{
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u32 gicconfig;
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/* Stop the counter */
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gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
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gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
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gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
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}
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#endif
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static bool gic_local_irq_is_routable(int intr)
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{
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u32 vpe_ctl;
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/* All local interrupts are routable in EIC mode. */
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if (cpu_has_veic)
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return true;
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vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
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switch (intr) {
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case GIC_LOCAL_INT_TIMER:
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return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
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case GIC_LOCAL_INT_PERFCTR:
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return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
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case GIC_LOCAL_INT_FDC:
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return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
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case GIC_LOCAL_INT_SWINT0:
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case GIC_LOCAL_INT_SWINT1:
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return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
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default:
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return true;
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}
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}
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static void gic_bind_eic_interrupt(int irq, int set)
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{
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/* Convert irq vector # to hw int # */
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irq -= GIC_PIN_TO_VEC_OFFSET;
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/* Set irq to use shadow set */
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
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GIC_VPE_EIC_SS(irq), set);
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}
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static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
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{
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irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
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gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(hwirq));
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}
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int gic_get_c0_compare_int(void)
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{
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if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
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return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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return irq_create_mapping(gic_irq_domain,
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GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
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}
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int gic_get_c0_perfcount_int(void)
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{
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if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
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/* Is the performance counter shared with the timer? */
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if (cp0_perfcount_irq < 0)
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return -1;
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return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
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}
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return irq_create_mapping(gic_irq_domain,
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GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
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}
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int gic_get_c0_fdc_int(void)
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{
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if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
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/* Is the FDC IRQ even present? */
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if (cp0_fdc_irq < 0)
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return -1;
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return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
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}
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return irq_create_mapping(gic_irq_domain,
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GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
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}
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int gic_get_usm_range(struct resource *gic_usm_res)
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{
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if (!gic_present)
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return -1;
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gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS;
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gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1);
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return 0;
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}
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static void gic_handle_shared_int(bool chained)
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{
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unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
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unsigned long *pcpu_mask;
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unsigned long pending_reg, intrmask_reg;
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DECLARE_BITMAP(pending, GIC_MAX_INTRS);
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DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
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/* Get per-cpu bitmaps */
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pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
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pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
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intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
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for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
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pending[i] = gic_read(pending_reg);
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intrmask[i] = gic_read(intrmask_reg);
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pending_reg += gic_reg_step;
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intrmask_reg += gic_reg_step;
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if (!config_enabled(CONFIG_64BIT) || mips_cm_is64)
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continue;
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pending[i] |= (u64)gic_read(pending_reg) << 32;
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intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
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pending_reg += gic_reg_step;
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intrmask_reg += gic_reg_step;
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}
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bitmap_and(pending, pending, intrmask, gic_shared_intrs);
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bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
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intr = find_first_bit(pending, gic_shared_intrs);
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while (intr != gic_shared_intrs) {
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virq = irq_linear_revmap(gic_irq_domain,
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GIC_SHARED_TO_HWIRQ(intr));
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if (chained)
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generic_handle_irq(virq);
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else
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do_IRQ(virq);
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/* go to next pending bit */
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bitmap_clear(pending, intr, 1);
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intr = find_first_bit(pending, gic_shared_intrs);
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}
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
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}
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static void gic_ack_irq(struct irq_data *d)
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{
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unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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unsigned long flags;
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bool is_edge;
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spin_lock_irqsave(&gic_lock, flags);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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gic_set_polarity(irq, GIC_POL_NEG);
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gic_set_trigger(irq, GIC_TRIG_EDGE);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = true;
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break;
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case IRQ_TYPE_EDGE_RISING:
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gic_set_polarity(irq, GIC_POL_POS);
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gic_set_trigger(irq, GIC_TRIG_EDGE);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = true;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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/* polarity is irrelevant in this case */
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gic_set_trigger(irq, GIC_TRIG_EDGE);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
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is_edge = true;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gic_set_polarity(irq, GIC_POL_NEG);
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gic_set_trigger(irq, GIC_TRIG_LEVEL);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = false;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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default:
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gic_set_polarity(irq, GIC_POL_POS);
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gic_set_trigger(irq, GIC_TRIG_LEVEL);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = false;
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break;
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}
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if (is_edge)
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irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
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handle_edge_irq, NULL);
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else
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irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
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handle_level_irq, NULL);
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spin_unlock_irqrestore(&gic_lock, flags);
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return 0;
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}
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#ifdef CONFIG_SMP
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
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bool force)
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{
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unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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cpumask_t tmp = CPU_MASK_NONE;
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unsigned long flags;
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int i;
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cpumask_and(&tmp, cpumask, cpu_online_mask);
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if (cpumask_empty(&tmp))
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return -EINVAL;
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/* Assumption : cpumask refers to a single CPU */
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spin_lock_irqsave(&gic_lock, flags);
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/* Re-route this IRQ */
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gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp)));
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|
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/* Update the pcpu_masks */
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for (i = 0; i < gic_vpes; i++)
|
|
clear_bit(irq, pcpu_masks[i].pcpu_mask);
|
|
set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask);
|
|
|
|
cpumask_copy(irq_data_get_affinity_mask(d), cpumask);
|
|
spin_unlock_irqrestore(&gic_lock, flags);
|
|
|
|
return IRQ_SET_MASK_OK_NOCOPY;
|
|
}
|
|
#endif
|
|
|
|
static struct irq_chip gic_level_irq_controller = {
|
|
.name = "MIPS GIC",
|
|
.irq_mask = gic_mask_irq,
|
|
.irq_unmask = gic_unmask_irq,
|
|
.irq_set_type = gic_set_type,
|
|
#ifdef CONFIG_SMP
|
|
.irq_set_affinity = gic_set_affinity,
|
|
#endif
|
|
};
|
|
|
|
static struct irq_chip gic_edge_irq_controller = {
|
|
.name = "MIPS GIC",
|
|
.irq_ack = gic_ack_irq,
|
|
.irq_mask = gic_mask_irq,
|
|
.irq_unmask = gic_unmask_irq,
|
|
.irq_set_type = gic_set_type,
|
|
#ifdef CONFIG_SMP
|
|
.irq_set_affinity = gic_set_affinity,
|
|
#endif
|
|
.ipi_send_single = gic_send_ipi,
|
|
};
|
|
|
|
static void gic_handle_local_int(bool chained)
|
|
{
|
|
unsigned long pending, masked;
|
|
unsigned int intr, virq;
|
|
|
|
pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
|
|
masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
|
|
|
|
bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
|
|
|
|
intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
|
|
while (intr != GIC_NUM_LOCAL_INTRS) {
|
|
virq = irq_linear_revmap(gic_irq_domain,
|
|
GIC_LOCAL_TO_HWIRQ(intr));
|
|
if (chained)
|
|
generic_handle_irq(virq);
|
|
else
|
|
do_IRQ(virq);
|
|
|
|
/* go to next pending bit */
|
|
bitmap_clear(&pending, intr, 1);
|
|
intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
|
|
}
|
|
}
|
|
|
|
static void gic_mask_local_irq(struct irq_data *d)
|
|
{
|
|
int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
|
|
|
|
gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
|
|
}
|
|
|
|
static void gic_unmask_local_irq(struct irq_data *d)
|
|
{
|
|
int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
|
|
|
|
gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
|
|
}
|
|
|
|
static struct irq_chip gic_local_irq_controller = {
|
|
.name = "MIPS GIC Local",
|
|
.irq_mask = gic_mask_local_irq,
|
|
.irq_unmask = gic_unmask_local_irq,
|
|
};
|
|
|
|
static void gic_mask_local_irq_all_vpes(struct irq_data *d)
|
|
{
|
|
int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
|
|
int i;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&gic_lock, flags);
|
|
for (i = 0; i < gic_vpes; i++) {
|
|
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
|
|
}
|
|
spin_unlock_irqrestore(&gic_lock, flags);
|
|
}
|
|
|
|
static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
|
|
{
|
|
int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
|
|
int i;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&gic_lock, flags);
|
|
for (i = 0; i < gic_vpes; i++) {
|
|
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
|
|
}
|
|
spin_unlock_irqrestore(&gic_lock, flags);
|
|
}
|
|
|
|
static struct irq_chip gic_all_vpes_local_irq_controller = {
|
|
.name = "MIPS GIC Local",
|
|
.irq_mask = gic_mask_local_irq_all_vpes,
|
|
.irq_unmask = gic_unmask_local_irq_all_vpes,
|
|
};
|
|
|
|
static void __gic_irq_dispatch(void)
|
|
{
|
|
gic_handle_local_int(false);
|
|
gic_handle_shared_int(false);
|
|
}
|
|
|
|
static void gic_irq_dispatch(struct irq_desc *desc)
|
|
{
|
|
gic_handle_local_int(true);
|
|
gic_handle_shared_int(true);
|
|
}
|
|
|
|
static void __init gic_basic_init(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
board_bind_eic_interrupt = &gic_bind_eic_interrupt;
|
|
|
|
/* Setup defaults */
|
|
for (i = 0; i < gic_shared_intrs; i++) {
|
|
gic_set_polarity(i, GIC_POL_POS);
|
|
gic_set_trigger(i, GIC_TRIG_LEVEL);
|
|
gic_reset_mask(i);
|
|
}
|
|
|
|
for (i = 0; i < gic_vpes; i++) {
|
|
unsigned int j;
|
|
|
|
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
|
for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
|
|
if (!gic_local_irq_is_routable(j))
|
|
continue;
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
int intr = GIC_HWIRQ_TO_LOCAL(hw);
|
|
int ret = 0;
|
|
int i;
|
|
unsigned long flags;
|
|
|
|
if (!gic_local_irq_is_routable(intr))
|
|
return -EPERM;
|
|
|
|
/*
|
|
* HACK: These are all really percpu interrupts, but the rest
|
|
* of the MIPS kernel code does not use the percpu IRQ API for
|
|
* the CP0 timer and performance counter interrupts.
|
|
*/
|
|
switch (intr) {
|
|
case GIC_LOCAL_INT_TIMER:
|
|
case GIC_LOCAL_INT_PERFCTR:
|
|
case GIC_LOCAL_INT_FDC:
|
|
irq_set_chip_and_handler(virq,
|
|
&gic_all_vpes_local_irq_controller,
|
|
handle_percpu_irq);
|
|
break;
|
|
default:
|
|
irq_set_chip_and_handler(virq,
|
|
&gic_local_irq_controller,
|
|
handle_percpu_devid_irq);
|
|
irq_set_percpu_devid(virq);
|
|
break;
|
|
}
|
|
|
|
spin_lock_irqsave(&gic_lock, flags);
|
|
for (i = 0; i < gic_vpes; i++) {
|
|
u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
|
|
|
|
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
|
|
|
switch (intr) {
|
|
case GIC_LOCAL_INT_WD:
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
|
|
break;
|
|
case GIC_LOCAL_INT_COMPARE:
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),
|
|
val);
|
|
break;
|
|
case GIC_LOCAL_INT_TIMER:
|
|
/* CONFIG_MIPS_CMP workaround (see __gic_init) */
|
|
val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
|
|
val);
|
|
break;
|
|
case GIC_LOCAL_INT_PERFCTR:
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
|
|
val);
|
|
break;
|
|
case GIC_LOCAL_INT_SWINT0:
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),
|
|
val);
|
|
break;
|
|
case GIC_LOCAL_INT_SWINT1:
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),
|
|
val);
|
|
break;
|
|
case GIC_LOCAL_INT_FDC:
|
|
gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
|
|
break;
|
|
default:
|
|
pr_err("Invalid local IRQ %d\n", intr);
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&gic_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
|
|
irq_hw_number_t hw, unsigned int vpe)
|
|
{
|
|
int intr = GIC_HWIRQ_TO_SHARED(hw);
|
|
unsigned long flags;
|
|
int i;
|
|
|
|
irq_set_chip_and_handler(virq, &gic_level_irq_controller,
|
|
handle_level_irq);
|
|
|
|
spin_lock_irqsave(&gic_lock, flags);
|
|
gic_map_to_pin(intr, gic_cpu_pin);
|
|
gic_map_to_vpe(intr, vpe);
|
|
for (i = 0; i < gic_vpes; i++)
|
|
clear_bit(intr, pcpu_masks[i].pcpu_mask);
|
|
set_bit(intr, pcpu_masks[vpe].pcpu_mask);
|
|
spin_unlock_irqrestore(&gic_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
|
|
return gic_local_irq_domain_map(d, virq, hw);
|
|
return gic_shared_irq_domain_map(d, virq, hw, 0);
|
|
}
|
|
|
|
static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs, void *arg)
|
|
{
|
|
struct gic_irq_spec *spec = arg;
|
|
irq_hw_number_t hwirq, base_hwirq;
|
|
int cpu, ret, i;
|
|
|
|
if (spec->type == GIC_DEVICE) {
|
|
/* verify that it doesn't conflict with an IPI irq */
|
|
if (test_bit(spec->hwirq, ipi_resrv))
|
|
return -EBUSY;
|
|
} else {
|
|
base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs);
|
|
if (base_hwirq == gic_shared_intrs) {
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* check that we have enough space */
|
|
for (i = base_hwirq; i < nr_irqs; i++) {
|
|
if (!test_bit(i, ipi_resrv))
|
|
return -EBUSY;
|
|
}
|
|
bitmap_clear(ipi_resrv, base_hwirq, nr_irqs);
|
|
|
|
/* map the hwirq for each cpu consecutively */
|
|
i = 0;
|
|
for_each_cpu(cpu, spec->ipimask) {
|
|
hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
|
|
|
|
ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
|
|
&gic_edge_irq_controller,
|
|
NULL);
|
|
if (ret)
|
|
goto error;
|
|
|
|
ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
|
|
if (ret)
|
|
goto error;
|
|
|
|
i++;
|
|
}
|
|
|
|
/*
|
|
* tell the parent about the base hwirq we allocated so it can
|
|
* set its own domain data
|
|
*/
|
|
spec->hwirq = base_hwirq;
|
|
}
|
|
|
|
return 0;
|
|
error:
|
|
bitmap_set(ipi_resrv, base_hwirq, nr_irqs);
|
|
return ret;
|
|
}
|
|
|
|
void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs)
|
|
{
|
|
irq_hw_number_t base_hwirq;
|
|
struct irq_data *data;
|
|
|
|
data = irq_get_irq_data(virq);
|
|
if (!data)
|
|
return;
|
|
|
|
base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
|
|
bitmap_set(ipi_resrv, base_hwirq, nr_irqs);
|
|
}
|
|
|
|
int gic_irq_domain_match(struct irq_domain *d, struct device_node *node,
|
|
enum irq_domain_bus_token bus_token)
|
|
{
|
|
/* this domain should'nt be accessed directly */
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops gic_irq_domain_ops = {
|
|
.map = gic_irq_domain_map,
|
|
.alloc = gic_irq_domain_alloc,
|
|
.free = gic_irq_domain_free,
|
|
.match = gic_irq_domain_match,
|
|
};
|
|
|
|
static int gic_dev_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
|
|
const u32 *intspec, unsigned int intsize,
|
|
irq_hw_number_t *out_hwirq,
|
|
unsigned int *out_type)
|
|
{
|
|
if (intsize != 3)
|
|
return -EINVAL;
|
|
|
|
if (intspec[0] == GIC_SHARED)
|
|
*out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
|
|
else if (intspec[0] == GIC_LOCAL)
|
|
*out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
|
|
else
|
|
return -EINVAL;
|
|
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gic_dev_domain_alloc(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs, void *arg)
|
|
{
|
|
struct irq_fwspec *fwspec = arg;
|
|
struct gic_irq_spec spec = {
|
|
.type = GIC_DEVICE,
|
|
.hwirq = fwspec->param[1],
|
|
};
|
|
int i, ret;
|
|
bool is_shared = fwspec->param[0] == GIC_SHARED;
|
|
|
|
if (is_shared) {
|
|
ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < nr_irqs; i++) {
|
|
irq_hw_number_t hwirq;
|
|
|
|
if (is_shared)
|
|
hwirq = GIC_SHARED_TO_HWIRQ(spec.hwirq + i);
|
|
else
|
|
hwirq = GIC_LOCAL_TO_HWIRQ(spec.hwirq + i);
|
|
|
|
ret = irq_domain_set_hwirq_and_chip(d, virq + i,
|
|
hwirq,
|
|
&gic_level_irq_controller,
|
|
NULL);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void gic_dev_domain_free(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs)
|
|
{
|
|
/* no real allocation is done for dev irqs, so no need to free anything */
|
|
return;
|
|
}
|
|
|
|
static struct irq_domain_ops gic_dev_domain_ops = {
|
|
.xlate = gic_dev_domain_xlate,
|
|
.alloc = gic_dev_domain_alloc,
|
|
.free = gic_dev_domain_free,
|
|
};
|
|
|
|
static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
|
|
const u32 *intspec, unsigned int intsize,
|
|
irq_hw_number_t *out_hwirq,
|
|
unsigned int *out_type)
|
|
{
|
|
/*
|
|
* There's nothing to translate here. hwirq is dynamically allocated and
|
|
* the irq type is always edge triggered.
|
|
* */
|
|
*out_hwirq = 0;
|
|
*out_type = IRQ_TYPE_EDGE_RISING;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs, void *arg)
|
|
{
|
|
struct cpumask *ipimask = arg;
|
|
struct gic_irq_spec spec = {
|
|
.type = GIC_IPI,
|
|
.ipimask = ipimask
|
|
};
|
|
int ret, i;
|
|
|
|
ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* the parent should have set spec.hwirq to the base_hwirq it allocated */
|
|
for (i = 0; i < nr_irqs; i++) {
|
|
ret = irq_domain_set_hwirq_and_chip(d, virq + i,
|
|
GIC_SHARED_TO_HWIRQ(spec.hwirq + i),
|
|
&gic_edge_irq_controller,
|
|
NULL);
|
|
if (ret)
|
|
goto error;
|
|
|
|
ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
|
|
if (ret)
|
|
goto error;
|
|
}
|
|
|
|
return 0;
|
|
error:
|
|
irq_domain_free_irqs_parent(d, virq, nr_irqs);
|
|
return ret;
|
|
}
|
|
|
|
void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs)
|
|
{
|
|
irq_domain_free_irqs_parent(d, virq, nr_irqs);
|
|
}
|
|
|
|
int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
|
|
enum irq_domain_bus_token bus_token)
|
|
{
|
|
bool is_ipi;
|
|
|
|
switch (bus_token) {
|
|
case DOMAIN_BUS_IPI:
|
|
is_ipi = d->bus_token == bus_token;
|
|
return to_of_node(d->fwnode) == node && is_ipi;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static struct irq_domain_ops gic_ipi_domain_ops = {
|
|
.xlate = gic_ipi_domain_xlate,
|
|
.alloc = gic_ipi_domain_alloc,
|
|
.free = gic_ipi_domain_free,
|
|
.match = gic_ipi_domain_match,
|
|
};
|
|
|
|
static void __init __gic_init(unsigned long gic_base_addr,
|
|
unsigned long gic_addrspace_size,
|
|
unsigned int cpu_vec, unsigned int irqbase,
|
|
struct device_node *node)
|
|
{
|
|
unsigned int gicconfig;
|
|
unsigned int v[2];
|
|
|
|
__gic_base_addr = gic_base_addr;
|
|
|
|
gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
|
|
|
|
gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
|
|
gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
|
|
GIC_SH_CONFIG_NUMINTRS_SHF;
|
|
gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
|
|
|
|
gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
|
|
GIC_SH_CONFIG_NUMVPES_SHF;
|
|
gic_vpes = gic_vpes + 1;
|
|
|
|
if (cpu_has_veic) {
|
|
/* Always use vector 1 in EIC mode */
|
|
gic_cpu_pin = 0;
|
|
timer_cpu_pin = gic_cpu_pin;
|
|
set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
|
|
__gic_irq_dispatch);
|
|
} else {
|
|
gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
|
|
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
|
|
gic_irq_dispatch);
|
|
/*
|
|
* With the CMP implementation of SMP (deprecated), other CPUs
|
|
* are started by the bootloader and put into a timer based
|
|
* waiting poll loop. We must not re-route those CPU's local
|
|
* timer interrupts as the wait instruction will never finish,
|
|
* so just handle whatever CPU interrupt it is routed to by
|
|
* default.
|
|
*
|
|
* This workaround should be removed when CMP support is
|
|
* dropped.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_MIPS_CMP) &&
|
|
gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
|
|
timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
|
|
GIC_VPE_TIMER_MAP)) &
|
|
GIC_MAP_MSK;
|
|
irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
|
|
GIC_CPU_PIN_OFFSET +
|
|
timer_cpu_pin,
|
|
gic_irq_dispatch);
|
|
} else {
|
|
timer_cpu_pin = gic_cpu_pin;
|
|
}
|
|
}
|
|
|
|
gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
|
|
gic_shared_intrs, irqbase,
|
|
&gic_irq_domain_ops, NULL);
|
|
if (!gic_irq_domain)
|
|
panic("Failed to add GIC IRQ domain");
|
|
|
|
gic_dev_domain = irq_domain_add_hierarchy(gic_irq_domain, 0,
|
|
GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
|
|
node, &gic_dev_domain_ops, NULL);
|
|
if (!gic_dev_domain)
|
|
panic("Failed to add GIC DEV domain");
|
|
|
|
gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
|
|
IRQ_DOMAIN_FLAG_IPI_PER_CPU,
|
|
GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
|
|
node, &gic_ipi_domain_ops, NULL);
|
|
if (!gic_ipi_domain)
|
|
panic("Failed to add GIC IPI domain");
|
|
|
|
gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
|
|
|
|
if (node &&
|
|
!of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
|
|
bitmap_set(ipi_resrv, v[0], v[1]);
|
|
} else {
|
|
/* Make the last 2 * gic_vpes available for IPIs */
|
|
bitmap_set(ipi_resrv,
|
|
gic_shared_intrs - 2 * gic_vpes,
|
|
2 * gic_vpes);
|
|
}
|
|
|
|
gic_basic_init();
|
|
}
|
|
|
|
void __init gic_init(unsigned long gic_base_addr,
|
|
unsigned long gic_addrspace_size,
|
|
unsigned int cpu_vec, unsigned int irqbase)
|
|
{
|
|
__gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
|
|
}
|
|
|
|
static int __init gic_of_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
struct resource res;
|
|
unsigned int cpu_vec, i = 0, reserved = 0;
|
|
phys_addr_t gic_base;
|
|
size_t gic_len;
|
|
|
|
/* Find the first available CPU vector. */
|
|
while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
|
|
i++, &cpu_vec))
|
|
reserved |= BIT(cpu_vec);
|
|
for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
|
|
if (!(reserved & BIT(cpu_vec)))
|
|
break;
|
|
}
|
|
if (cpu_vec == 8) {
|
|
pr_err("No CPU vectors available for GIC\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_address_to_resource(node, 0, &res)) {
|
|
/*
|
|
* Probe the CM for the GIC base address if not specified
|
|
* in the device-tree.
|
|
*/
|
|
if (mips_cm_present()) {
|
|
gic_base = read_gcr_gic_base() &
|
|
~CM_GCR_GIC_BASE_GICEN_MSK;
|
|
gic_len = 0x20000;
|
|
} else {
|
|
pr_err("Failed to get GIC memory range\n");
|
|
return -ENODEV;
|
|
}
|
|
} else {
|
|
gic_base = res.start;
|
|
gic_len = resource_size(&res);
|
|
}
|
|
|
|
if (mips_cm_present())
|
|
write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
|
|
gic_present = true;
|
|
|
|
__gic_init(gic_base, gic_len, cpu_vec, 0, node);
|
|
|
|
return 0;
|
|
}
|
|
IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
|