142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Turbo Boost Max Technology 3.0 legacy (non HWP) enumeration driver
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* Copyright (c) 2017, Intel Corporation.
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* All rights reserved.
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*
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* Author: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/cpufeature.h>
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#include <linux/cpuhotplug.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/topology.h>
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#include <linux/workqueue.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#define MSR_OC_MAILBOX 0x150
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#define MSR_OC_MAILBOX_CMD_OFFSET 32
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#define MSR_OC_MAILBOX_RSP_OFFSET 32
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#define MSR_OC_MAILBOX_BUSY_BIT 63
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#define OC_MAILBOX_FC_CONTROL_CMD 0x1C
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/*
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* Typical latency to get mail box response is ~3us, It takes +3 us to
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* process reading mailbox after issuing mailbox write on a Broadwell 3.4 GHz
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* system. So for most of the time, the first mailbox read should have the
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* response, but to avoid some boundary cases retry twice.
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*/
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#define OC_MAILBOX_RETRY_COUNT 2
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static int get_oc_core_priority(unsigned int cpu)
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{
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u64 value, cmd = OC_MAILBOX_FC_CONTROL_CMD;
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int ret, i;
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/* Issue favored core read command */
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value = cmd << MSR_OC_MAILBOX_CMD_OFFSET;
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/* Set the busy bit to indicate OS is trying to issue command */
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value |= BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT);
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ret = wrmsrl_safe(MSR_OC_MAILBOX, value);
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if (ret) {
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pr_debug("cpu %d OC mailbox write failed\n", cpu);
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return ret;
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}
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for (i = 0; i < OC_MAILBOX_RETRY_COUNT; ++i) {
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ret = rdmsrl_safe(MSR_OC_MAILBOX, &value);
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if (ret) {
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pr_debug("cpu %d OC mailbox read failed\n", cpu);
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break;
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}
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if (value & BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT)) {
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pr_debug("cpu %d OC mailbox still processing\n", cpu);
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ret = -EBUSY;
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continue;
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}
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if ((value >> MSR_OC_MAILBOX_RSP_OFFSET) & 0xff) {
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pr_debug("cpu %d OC mailbox cmd failed\n", cpu);
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ret = -ENXIO;
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break;
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}
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ret = value & 0xff;
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pr_debug("cpu %d max_ratio %d\n", cpu, ret);
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break;
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}
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return ret;
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}
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/*
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* The work item is needed to avoid CPU hotplug locking issues. The function
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* itmt_legacy_set_priority() is called from CPU online callback, so can't
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* call sched_set_itmt_support() from there as this function will aquire
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* hotplug locks in its path.
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*/
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static void itmt_legacy_work_fn(struct work_struct *work)
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{
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sched_set_itmt_support();
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}
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static DECLARE_WORK(sched_itmt_work, itmt_legacy_work_fn);
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static int itmt_legacy_cpu_online(unsigned int cpu)
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{
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static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
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int priority;
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priority = get_oc_core_priority(cpu);
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if (priority < 0)
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return 0;
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sched_set_itmt_core_prio(priority, cpu);
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/* Enable ITMT feature when a core with different priority is found */
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if (max_highest_perf <= min_highest_perf) {
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if (priority > max_highest_perf)
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max_highest_perf = priority;
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if (priority < min_highest_perf)
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min_highest_perf = priority;
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if (max_highest_perf > min_highest_perf)
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schedule_work(&sched_itmt_work);
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}
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return 0;
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}
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#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
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static const struct x86_cpu_id itmt_legacy_cpu_ids[] = {
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ICPU(INTEL_FAM6_BROADWELL_X),
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ICPU(INTEL_FAM6_SKYLAKE_X),
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{}
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};
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static int __init itmt_legacy_init(void)
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{
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const struct x86_cpu_id *id;
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int ret;
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id = x86_match_cpu(itmt_legacy_cpu_ids);
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if (!id)
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return -ENODEV;
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"platform/x86/turbo_max_3:online",
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itmt_legacy_cpu_online, NULL);
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if (ret < 0)
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return ret;
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return 0;
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}
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late_initcall(itmt_legacy_init)
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