193 lines
5.3 KiB
C
193 lines
5.3 KiB
C
/*
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* linux/arch/arm/mach-omap2/usb-ehci.c
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*
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* This file will contain the board specific details for the
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* Synopsys EHCI host controller on OMAP3430
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*
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* Copyright (C) 2007 Texas Instruments
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* Author: Vikram Pandita <vikram.pandita@ti.com>
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*
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* Generalization by:
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* Felipe Balbi <felipe.balbi@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <plat/mux.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <plat/usb.h>
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#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
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static struct resource ehci_resources[] = {
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{
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.start = OMAP34XX_EHCI_BASE,
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.end = OMAP34XX_EHCI_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP34XX_UHH_CONFIG_BASE,
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.end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP34XX_USBTLL_BASE,
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.end = OMAP34XX_USBTLL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{ /* general IRQ */
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.start = INT_34XX_EHCI_IRQ,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 ehci_dmamask = ~(u32)0;
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static struct platform_device ehci_device = {
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.name = "ehci-omap",
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.id = 0,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = NULL,
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},
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.num_resources = ARRAY_SIZE(ehci_resources),
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.resource = ehci_resources,
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};
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/* MUX settings for EHCI pins */
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/*
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* setup_ehci_io_mux - initialize IO pad mux for USBHOST
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*/
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static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
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{
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switch (port_mode[0]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
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omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
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omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
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omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
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omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
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omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
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omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
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omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
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omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
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omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
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omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
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omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
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omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
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omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
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omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
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omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
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omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
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omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
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omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
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omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
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omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
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omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
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omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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/* FALLTHROUGH */
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default:
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break;
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}
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switch (port_mode[1]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
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omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
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omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
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omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
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omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
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omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
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omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
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omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
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omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
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omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
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omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
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omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
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omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
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omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
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omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
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omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
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omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
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omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
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omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
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omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
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omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
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omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
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omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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/* FALLTHROUGH */
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default:
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break;
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}
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switch (port_mode[2]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
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omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
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omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
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omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
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omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
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omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
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omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
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omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
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omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
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omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
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omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
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omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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/* FALLTHROUGH */
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default:
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break;
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}
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return;
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}
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void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
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{
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platform_device_add_data(&ehci_device, pdata, sizeof(*pdata));
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/* Setup Pin IO MUX for EHCI */
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if (cpu_is_omap34xx())
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setup_ehci_io_mux(pdata->port_mode);
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if (platform_device_register(&ehci_device) < 0) {
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printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
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return;
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}
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}
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#else
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void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
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{
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}
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#endif /* CONFIG_USB_EHCI_HCD */
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