386 lines
12 KiB
C
386 lines
12 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2012 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2012 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copy
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Intel PCIe NTB Linux driver
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*
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* Contact Information:
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* Jon Mason <jon.mason@intel.com>
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*/
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#include <linux/ntb_transport.h>
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#define NTB_LINK_STATUS_ACTIVE 0x2000
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#define NTB_LINK_SPEED_MASK 0x000f
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#define NTB_LINK_WIDTH_MASK 0x03f0
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#define SNB_MSIX_CNT 4
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#define SNB_MAX_B2B_SPADS 16
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#define SNB_MAX_COMPAT_SPADS 16
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/* Reserve the uppermost bit for link interrupt */
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#define SNB_MAX_DB_BITS 15
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#define SNB_LINK_DB 15
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#define SNB_DB_BITS_PER_VEC 5
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#define HSX_SPLITBAR_MAX_MW 3
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#define SNB_MAX_MW 2
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#define SNB_ERRATA_MAX_MW 1
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#define SNB_DB_HW_LINK 0x8000
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#define SNB_UNCERRSTS_OFFSET 0x014C
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#define SNB_CORERRSTS_OFFSET 0x0158
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#define SNB_LINK_STATUS_OFFSET 0x01A2
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#define SNB_PCICMD_OFFSET 0x0504
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#define SNB_DEVCTRL_OFFSET 0x0598
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#define SNB_DEVSTS_OFFSET 0x059A
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#define SNB_SLINK_STATUS_OFFSET 0x05A2
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#define SNB_PBAR2LMT_OFFSET 0x0000
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#define SNB_PBAR4LMT_OFFSET 0x0008
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#define SNB_PBAR5LMT_OFFSET 0x000C
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#define SNB_PBAR2XLAT_OFFSET 0x0010
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#define SNB_PBAR4XLAT_OFFSET 0x0018
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#define SNB_PBAR5XLAT_OFFSET 0x001C
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#define SNB_SBAR2LMT_OFFSET 0x0020
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#define SNB_SBAR4LMT_OFFSET 0x0028
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#define SNB_SBAR5LMT_OFFSET 0x002C
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#define SNB_SBAR2XLAT_OFFSET 0x0030
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#define SNB_SBAR4XLAT_OFFSET 0x0038
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#define SNB_SBAR5XLAT_OFFSET 0x003C
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#define SNB_SBAR0BASE_OFFSET 0x0040
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#define SNB_SBAR2BASE_OFFSET 0x0048
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#define SNB_SBAR4BASE_OFFSET 0x0050
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#define SNB_SBAR5BASE_OFFSET 0x0054
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#define SNB_NTBCNTL_OFFSET 0x0058
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#define SNB_SBDF_OFFSET 0x005C
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#define SNB_PDOORBELL_OFFSET 0x0060
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#define SNB_PDBMSK_OFFSET 0x0062
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#define SNB_SDOORBELL_OFFSET 0x0064
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#define SNB_SDBMSK_OFFSET 0x0066
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#define SNB_USMEMMISS_OFFSET 0x0070
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#define SNB_SPAD_OFFSET 0x0080
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#define SNB_SPADSEMA4_OFFSET 0x00c0
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#define SNB_WCCNTRL_OFFSET 0x00e0
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#define SNB_B2B_SPAD_OFFSET 0x0100
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#define SNB_B2B_DOORBELL_OFFSET 0x0140
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#define SNB_B2B_XLAT_OFFSETL 0x0144
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#define SNB_B2B_XLAT_OFFSETU 0x0148
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/*
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* The addresses are setup so the 32bit BARs can function. Thus
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* the addresses are all in 32bit space
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*/
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#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL
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#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL
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#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL
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#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL
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#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL
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#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL
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#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL
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#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL
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#define BWD_MSIX_CNT 34
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#define BWD_MAX_SPADS 16
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#define BWD_MAX_DB_BITS 34
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#define BWD_DB_BITS_PER_VEC 1
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#define BWD_MAX_MW 2
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#define BWD_PCICMD_OFFSET 0xb004
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#define BWD_MBAR23_OFFSET 0xb018
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#define BWD_MBAR45_OFFSET 0xb020
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#define BWD_DEVCTRL_OFFSET 0xb048
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#define BWD_LINK_STATUS_OFFSET 0xb052
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#define BWD_ERRCORSTS_OFFSET 0xb110
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#define BWD_SBAR2XLAT_OFFSET 0x0008
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#define BWD_SBAR4XLAT_OFFSET 0x0010
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#define BWD_PDOORBELL_OFFSET 0x0020
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#define BWD_PDBMSK_OFFSET 0x0028
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#define BWD_NTBCNTL_OFFSET 0x0060
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#define BWD_EBDF_OFFSET 0x0064
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#define BWD_SPAD_OFFSET 0x0080
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#define BWD_SPADSEMA_OFFSET 0x00c0
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#define BWD_STKYSPAD_OFFSET 0x00c4
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#define BWD_PBAR2XLAT_OFFSET 0x8008
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#define BWD_PBAR4XLAT_OFFSET 0x8010
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#define BWD_B2B_DOORBELL_OFFSET 0x8020
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#define BWD_B2B_SPAD_OFFSET 0x8080
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#define BWD_B2B_SPADSEMA_OFFSET 0x80c0
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#define BWD_B2B_STKYSPAD_OFFSET 0x80c4
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#define BWD_MODPHY_PCSREG4 0x1c004
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#define BWD_MODPHY_PCSREG6 0x1c006
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#define BWD_IP_BASE 0xC000
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#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024)
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#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
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#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040)
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#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324)
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#define BWD_DESKEWSTS_DBERR (1 << 15)
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#define BWD_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
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#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
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#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
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#define NTB_CNTL_CFG_LOCK (1 << 0)
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#define NTB_CNTL_LINK_DISABLE (1 << 1)
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#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
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#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
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#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
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#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
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#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
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#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
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#define BWD_CNTL_LINK_DOWN (1 << 16)
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#define NTB_PPD_OFFSET 0x00D4
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#define SNB_PPD_CONN_TYPE 0x0003
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#define SNB_PPD_DEV_TYPE 0x0010
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#define SNB_PPD_SPLIT_BAR (1 << 6)
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#define BWD_PPD_INIT_LINK 0x0008
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#define BWD_PPD_CONN_TYPE 0x0300
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#define BWD_PPD_DEV_TYPE 0x1000
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
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#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
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#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
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#ifndef readq
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static inline u64 readq(void __iomem *addr)
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{
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return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
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}
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#endif
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#ifndef writeq
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static inline void writeq(u64 val, void __iomem *addr)
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{
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writel(val & 0xffffffff, addr);
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writel(val >> 32, addr + 4);
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}
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#endif
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#define NTB_BAR_MMIO 0
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#define NTB_BAR_23 2
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#define NTB_BAR_4 4
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#define NTB_BAR_5 5
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#define NTB_BAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\
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(1 << NTB_BAR_4))
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#define NTB_SPLITBAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\
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(1 << NTB_BAR_4) | (1 << NTB_BAR_5))
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#define NTB_HB_TIMEOUT msecs_to_jiffies(1000)
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enum ntb_hw_event {
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NTB_EVENT_SW_EVENT0 = 0,
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NTB_EVENT_SW_EVENT1,
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NTB_EVENT_SW_EVENT2,
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NTB_EVENT_HW_ERROR,
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NTB_EVENT_HW_LINK_UP,
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NTB_EVENT_HW_LINK_DOWN,
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};
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struct ntb_mw {
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dma_addr_t phys_addr;
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void __iomem *vbase;
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resource_size_t bar_sz;
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};
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struct ntb_db_cb {
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int (*callback)(void *data, int db_num);
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unsigned int db_num;
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void *data;
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struct ntb_device *ndev;
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struct tasklet_struct irq_work;
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};
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#define WA_SNB_ERR 0x00000001
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struct ntb_device {
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struct pci_dev *pdev;
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struct msix_entry *msix_entries;
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void __iomem *reg_base;
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struct ntb_mw *mw;
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struct {
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unsigned char max_mw;
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unsigned char max_spads;
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unsigned char max_db_bits;
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unsigned char msix_cnt;
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} limits;
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struct {
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void __iomem *ldb;
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void __iomem *ldb_mask;
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void __iomem *rdb;
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void __iomem *bar2_xlat;
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void __iomem *bar4_xlat;
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void __iomem *bar5_xlat;
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void __iomem *spad_write;
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void __iomem *spad_read;
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void __iomem *lnk_cntl;
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void __iomem *lnk_stat;
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void __iomem *spci_cmd;
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} reg_ofs;
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struct ntb_transport *ntb_transport;
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void (*event_cb)(void *handle, enum ntb_hw_event event);
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struct ntb_db_cb *db_cb;
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unsigned char hw_type;
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unsigned char conn_type;
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unsigned char dev_type;
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unsigned char num_msix;
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unsigned char bits_per_vector;
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unsigned char max_cbs;
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unsigned char link_width;
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unsigned char link_speed;
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unsigned char link_status;
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unsigned char split_bar;
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struct delayed_work hb_timer;
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unsigned long last_ts;
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struct delayed_work lr_timer;
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struct dentry *debugfs_dir;
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struct dentry *debugfs_info;
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unsigned int wa_flags;
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};
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/**
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* ntb_max_cbs() - return the max callbacks
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* @ndev: pointer to ntb_device instance
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*
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* Given the ntb pointer, return the maximum number of callbacks
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*
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* RETURNS: the maximum number of callbacks
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*/
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static inline unsigned char ntb_max_cbs(struct ntb_device *ndev)
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{
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return ndev->max_cbs;
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}
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/**
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* ntb_max_mw() - return the max number of memory windows
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* @ndev: pointer to ntb_device instance
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*
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* Given the ntb pointer, return the maximum number of memory windows
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*
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* RETURNS: the maximum number of memory windows
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*/
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static inline unsigned char ntb_max_mw(struct ntb_device *ndev)
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{
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return ndev->limits.max_mw;
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}
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/**
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* ntb_hw_link_status() - return the hardware link status
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* @ndev: pointer to ntb_device instance
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*
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* Returns true if the hardware is connected to the remote system
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*
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* RETURNS: true or false based on the hardware link state
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*/
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static inline bool ntb_hw_link_status(struct ntb_device *ndev)
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{
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return ndev->link_status == NTB_LINK_UP;
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}
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/**
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* ntb_query_pdev() - return the pci_dev pointer
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* @ndev: pointer to ntb_device instance
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*
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* Given the ntb pointer, return the pci_dev pointer for the NTB hardware device
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*
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* RETURNS: a pointer to the ntb pci_dev
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*/
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static inline struct pci_dev *ntb_query_pdev(struct ntb_device *ndev)
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{
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return ndev->pdev;
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}
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/**
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* ntb_query_debugfs() - return the debugfs pointer
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* @ndev: pointer to ntb_device instance
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*
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* Given the ntb pointer, return the debugfs directory pointer for the NTB
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* hardware device
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*
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* RETURNS: a pointer to the debugfs directory
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*/
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static inline struct dentry *ntb_query_debugfs(struct ntb_device *ndev)
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{
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return ndev->debugfs_dir;
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}
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struct ntb_device *ntb_register_transport(struct pci_dev *pdev,
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void *transport);
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void ntb_unregister_transport(struct ntb_device *ndev);
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void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr);
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int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
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void *data, int (*db_cb_func)(void *data,
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int db_num));
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void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx);
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int ntb_register_event_callback(struct ntb_device *ndev,
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void (*event_cb_func)(void *handle,
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enum ntb_hw_event event));
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void ntb_unregister_event_callback(struct ntb_device *ndev);
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int ntb_get_max_spads(struct ntb_device *ndev);
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int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val);
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int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);
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int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val);
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int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);
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resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw);
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void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw);
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u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw);
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void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int idx);
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void *ntb_find_transport(struct pci_dev *pdev);
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int ntb_transport_init(struct pci_dev *pdev);
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void ntb_transport_free(void *transport);
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