130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* TSC frequency enumeration via MSR
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*
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* Copyright (C) 2013, 2018 Intel Corporation
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* Author: Bin Gao <bin.gao@intel.com>
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*/
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#include <linux/kernel.h>
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#include <asm/apic.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/msr.h>
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#include <asm/param.h>
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#include <asm/tsc.h>
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#define MAX_NUM_FREQS 9
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/*
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* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
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* read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
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* Unfortunately some Intel Atom SoCs aren't quite compliant to this,
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* so we need manually differentiate SoC families. This is what the
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* field msr_plat does.
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*/
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struct freq_desc {
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u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
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u32 freqs[MAX_NUM_FREQS];
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};
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/*
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* Penwell and Clovertrail use spread spectrum clock,
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* so the freq number is not exactly the same as reported
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* by MSR based on SDM.
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*/
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static const struct freq_desc freq_desc_pnw = {
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0, { 0, 0, 0, 0, 0, 99840, 0, 83200 }
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};
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static const struct freq_desc freq_desc_clv = {
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0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 }
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};
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static const struct freq_desc freq_desc_byt = {
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1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 }
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};
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static const struct freq_desc freq_desc_cht = {
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1, { 83300, 100000, 133300, 116700, 80000, 93300, 90000, 88900, 87500 }
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};
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static const struct freq_desc freq_desc_tng = {
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1, { 0, 100000, 133300, 0, 0, 0, 0, 0 }
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};
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static const struct freq_desc freq_desc_ann = {
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1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
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};
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static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
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INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw),
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INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv),
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INTEL_CPU_FAM6(ATOM_SILVERMONT, freq_desc_byt),
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INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
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INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht),
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INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann),
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{}
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};
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/*
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* MSR-based CPU/TSC frequency discovery for certain CPUs.
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*
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* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
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* Return processor base frequency in KHz, or 0 on failure.
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*/
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unsigned long cpu_khz_from_msr(void)
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{
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u32 lo, hi, ratio, freq;
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const struct freq_desc *freq_desc;
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const struct x86_cpu_id *id;
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unsigned long res;
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id = x86_match_cpu(tsc_msr_cpu_ids);
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if (!id)
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return 0;
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freq_desc = (struct freq_desc *)id->driver_data;
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if (freq_desc->msr_plat) {
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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ratio = (lo >> 8) & 0xff;
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} else {
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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ratio = (hi >> 8) & 0x1f;
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}
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
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freq = freq_desc->freqs[lo & 0x7];
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/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
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res = freq * ratio;
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#ifdef CONFIG_X86_LOCAL_APIC
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lapic_timer_frequency = (freq * 1000) / HZ;
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#endif
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/*
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* TSC frequency determined by MSR is always considered "known"
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* because it is reported by HW.
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* Another fact is that on MSR capable platforms, PIT/HPET is
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* generally not available so calibration won't work at all.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
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/*
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* Unfortunately there is no way for hardware to tell whether the
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* TSC is reliable. We were told by silicon design team that TSC
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* on Atom SoCs are always "reliable". TSC is also the only
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* reliable clocksource on these SoCs (HPET is either not present
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* or not functional) so mark TSC reliable which removes the
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* requirement for a watchdog clocksource.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
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return res;
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}
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