761 lines
17 KiB
C
761 lines
17 KiB
C
/*
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* Copyright 2008-2011 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/xics.h>
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#include "wsp.h"
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#include "ics.h"
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/* WSP ICS */
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struct wsp_ics {
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struct ics ics;
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struct device_node *dn;
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void __iomem *regs;
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spinlock_t lock;
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unsigned long *bitmap;
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u32 chip_id;
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u32 lsi_base;
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u32 lsi_count;
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u64 hwirq_start;
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u64 count;
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#ifdef CONFIG_SMP
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int *hwirq_cpu_map;
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#endif
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};
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#define to_wsp_ics(ics) container_of(ics, struct wsp_ics, ics)
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#define INT_SRC_LAYER_BUID_REG(base) ((base) + 0x00)
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#define IODA_TBL_ADDR_REG(base) ((base) + 0x18)
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#define IODA_TBL_DATA_REG(base) ((base) + 0x20)
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#define XIVE_UPDATE_REG(base) ((base) + 0x28)
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#define ICS_INT_CAPS_REG(base) ((base) + 0x30)
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#define TBL_AUTO_INCREMENT ((1UL << 63) | (1UL << 15))
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#define TBL_SELECT_XIST (1UL << 48)
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#define TBL_SELECT_XIVT (1UL << 49)
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#define IODA_IRQ(irq) ((irq) & (0x7FFULL)) /* HRM 5.1.3.4 */
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#define XIST_REQUIRED 0x8
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#define XIST_REJECTED 0x4
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#define XIST_PRESENTED 0x2
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#define XIST_PENDING 0x1
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#define XIVE_SERVER_SHIFT 42
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#define XIVE_SERVER_MASK 0xFFFFULL
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#define XIVE_PRIORITY_MASK 0xFFULL
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#define XIVE_PRIORITY_SHIFT 32
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#define XIVE_WRITE_ENABLE (1ULL << 63)
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/*
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* The docs refer to a 6 bit field called ChipID, which consists of a
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* 3 bit NodeID and a 3 bit ChipID. On WSP the ChipID is always zero
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* so we ignore it, and every where we use "chip id" in this code we
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* mean the NodeID.
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*/
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#define WSP_ICS_CHIP_SHIFT 17
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static struct wsp_ics *ics_list;
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static int num_ics;
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/* ICS Source controller accessors */
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static u64 wsp_ics_get_xive(struct wsp_ics *ics, unsigned int irq)
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{
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unsigned long flags;
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u64 xive;
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spin_lock_irqsave(&ics->lock, flags);
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out_be64(IODA_TBL_ADDR_REG(ics->regs), TBL_SELECT_XIVT | IODA_IRQ(irq));
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xive = in_be64(IODA_TBL_DATA_REG(ics->regs));
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spin_unlock_irqrestore(&ics->lock, flags);
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return xive;
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}
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static void wsp_ics_set_xive(struct wsp_ics *ics, unsigned int irq, u64 xive)
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{
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xive &= ~XIVE_ADDR_MASK;
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xive |= (irq & XIVE_ADDR_MASK);
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xive |= XIVE_WRITE_ENABLE;
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out_be64(XIVE_UPDATE_REG(ics->regs), xive);
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}
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static u64 xive_set_server(u64 xive, unsigned int server)
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{
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u64 mask = ~(XIVE_SERVER_MASK << XIVE_SERVER_SHIFT);
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xive &= mask;
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xive |= (server & XIVE_SERVER_MASK) << XIVE_SERVER_SHIFT;
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return xive;
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}
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static u64 xive_set_priority(u64 xive, unsigned int priority)
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{
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u64 mask = ~(XIVE_PRIORITY_MASK << XIVE_PRIORITY_SHIFT);
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xive &= mask;
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xive |= (priority & XIVE_PRIORITY_MASK) << XIVE_PRIORITY_SHIFT;
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return xive;
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}
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#ifdef CONFIG_SMP
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/* Find logical CPUs within mask on a given chip and store result in ret */
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void cpus_on_chip(int chip_id, cpumask_t *mask, cpumask_t *ret)
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{
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int cpu, chip;
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struct device_node *cpu_dn, *dn;
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const u32 *prop;
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cpumask_clear(ret);
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for_each_cpu(cpu, mask) {
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cpu_dn = of_get_cpu_node(cpu, NULL);
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if (!cpu_dn)
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continue;
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prop = of_get_property(cpu_dn, "at-node", NULL);
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if (!prop) {
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of_node_put(cpu_dn);
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continue;
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}
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dn = of_find_node_by_phandle(*prop);
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of_node_put(cpu_dn);
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chip = wsp_get_chip_id(dn);
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if (chip == chip_id)
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cpumask_set_cpu(cpu, ret);
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of_node_put(dn);
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}
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}
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/* Store a suitable CPU to handle a hwirq in the ics->hwirq_cpu_map cache */
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static int cache_hwirq_map(struct wsp_ics *ics, unsigned int hwirq,
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const cpumask_t *affinity)
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{
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cpumask_var_t avail, newmask;
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int ret = -ENOMEM, cpu, cpu_rover = 0, target;
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int index = hwirq - ics->hwirq_start;
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unsigned int nodeid;
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BUG_ON(index < 0 || index >= ics->count);
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if (!ics->hwirq_cpu_map)
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return -ENOMEM;
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if (!distribute_irqs) {
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ics->hwirq_cpu_map[hwirq - ics->hwirq_start] = xics_default_server;
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return 0;
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}
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/* Allocate needed CPU masks */
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if (!alloc_cpumask_var(&avail, GFP_KERNEL))
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goto ret;
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if (!alloc_cpumask_var(&newmask, GFP_KERNEL))
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goto freeavail;
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/* Find PBus attached to the source of this IRQ */
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nodeid = (hwirq >> WSP_ICS_CHIP_SHIFT) & 0x3; /* 12:14 */
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/* Find CPUs that could handle this IRQ */
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if (affinity)
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cpumask_and(avail, cpu_online_mask, affinity);
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else
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cpumask_copy(avail, cpu_online_mask);
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/* Narrow selection down to logical CPUs on the same chip */
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cpus_on_chip(nodeid, avail, newmask);
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/* Ensure we haven't narrowed it down to 0 */
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if (unlikely(cpumask_empty(newmask))) {
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if (unlikely(cpumask_empty(avail))) {
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ret = -1;
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goto out;
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}
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cpumask_copy(newmask, avail);
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}
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/* Choose a CPU out of those we narrowed it down to in round robin */
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target = hwirq % cpumask_weight(newmask);
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for_each_cpu(cpu, newmask) {
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if (cpu_rover++ >= target) {
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ics->hwirq_cpu_map[index] = get_hard_smp_processor_id(cpu);
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ret = 0;
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goto out;
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}
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}
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/* Shouldn't happen */
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WARN_ON(1);
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out:
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free_cpumask_var(newmask);
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freeavail:
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free_cpumask_var(avail);
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ret:
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if (ret < 0) {
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ics->hwirq_cpu_map[index] = cpumask_first(cpu_online_mask);
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pr_warning("Error, falling hwirq 0x%x routing back to CPU %i\n",
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hwirq, ics->hwirq_cpu_map[index]);
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}
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return ret;
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}
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static void alloc_irq_map(struct wsp_ics *ics)
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{
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int i;
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ics->hwirq_cpu_map = kmalloc(sizeof(int) * ics->count, GFP_KERNEL);
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if (!ics->hwirq_cpu_map) {
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pr_warning("Allocate hwirq_cpu_map failed, "
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"IRQ balancing disabled\n");
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return;
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}
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for (i=0; i < ics->count; i++)
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ics->hwirq_cpu_map[i] = xics_default_server;
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}
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static int get_irq_server(struct wsp_ics *ics, unsigned int hwirq)
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{
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int index = hwirq - ics->hwirq_start;
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BUG_ON(index < 0 || index >= ics->count);
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if (!ics->hwirq_cpu_map)
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return xics_default_server;
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return ics->hwirq_cpu_map[index];
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}
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#else /* !CONFIG_SMP */
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static int cache_hwirq_map(struct wsp_ics *ics, unsigned int hwirq,
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const cpumask_t *affinity)
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{
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return 0;
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}
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static int get_irq_server(struct wsp_ics *ics, unsigned int hwirq)
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{
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return xics_default_server;
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}
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static void alloc_irq_map(struct wsp_ics *ics) { }
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#endif
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static void wsp_chip_unmask_irq(struct irq_data *d)
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{
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unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
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struct wsp_ics *ics;
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int server;
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u64 xive;
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if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
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return;
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ics = d->chip_data;
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if (WARN_ON(!ics))
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return;
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server = get_irq_server(ics, hw_irq);
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xive = wsp_ics_get_xive(ics, hw_irq);
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xive = xive_set_server(xive, server);
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xive = xive_set_priority(xive, DEFAULT_PRIORITY);
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wsp_ics_set_xive(ics, hw_irq, xive);
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}
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static unsigned int wsp_chip_startup(struct irq_data *d)
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{
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/* unmask it */
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wsp_chip_unmask_irq(d);
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return 0;
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}
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static void wsp_mask_real_irq(unsigned int hw_irq, struct wsp_ics *ics)
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{
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u64 xive;
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if (hw_irq == XICS_IPI)
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return;
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if (WARN_ON(!ics))
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return;
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xive = wsp_ics_get_xive(ics, hw_irq);
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xive = xive_set_server(xive, xics_default_server);
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xive = xive_set_priority(xive, LOWEST_PRIORITY);
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wsp_ics_set_xive(ics, hw_irq, xive);
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}
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static void wsp_chip_mask_irq(struct irq_data *d)
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{
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unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
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struct wsp_ics *ics = d->chip_data;
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if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
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return;
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wsp_mask_real_irq(hw_irq, ics);
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}
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static int wsp_chip_set_affinity(struct irq_data *d,
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const struct cpumask *cpumask, bool force)
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{
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unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
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struct wsp_ics *ics;
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int ret;
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u64 xive;
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if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
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return -1;
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ics = d->chip_data;
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if (WARN_ON(!ics))
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return -1;
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xive = wsp_ics_get_xive(ics, hw_irq);
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/*
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* For the moment only implement delivery to all cpus or one cpu.
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* Get current irq_server for the given irq
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*/
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ret = cache_hwirq_map(ics, d->irq, cpumask);
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if (ret == -1) {
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char cpulist[128];
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cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
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pr_warning("%s: No online cpus in the mask %s for irq %d\n",
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__func__, cpulist, d->irq);
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return -1;
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} else if (ret == -ENOMEM) {
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pr_warning("%s: Out of memory\n", __func__);
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return -1;
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}
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xive = xive_set_server(xive, get_irq_server(ics, hw_irq));
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wsp_ics_set_xive(ics, hw_irq, xive);
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return 0;
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}
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static struct irq_chip wsp_irq_chip = {
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.name = "WSP ICS",
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.irq_startup = wsp_chip_startup,
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.irq_mask = wsp_chip_mask_irq,
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.irq_unmask = wsp_chip_unmask_irq,
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.irq_set_affinity = wsp_chip_set_affinity
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};
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static int wsp_ics_host_match(struct ics *ics, struct device_node *dn)
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{
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/* All ICSs in the system implement a global irq number space,
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* so match against them all. */
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return of_device_is_compatible(dn, "ibm,ppc-xics");
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}
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static int wsp_ics_match_hwirq(struct wsp_ics *wsp_ics, unsigned int hwirq)
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{
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if (hwirq >= wsp_ics->hwirq_start &&
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hwirq < wsp_ics->hwirq_start + wsp_ics->count)
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return 1;
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return 0;
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}
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static int wsp_ics_map(struct ics *ics, unsigned int virq)
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{
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struct wsp_ics *wsp_ics = to_wsp_ics(ics);
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unsigned int hw_irq = virq_to_hw(virq);
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unsigned long flags;
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if (!wsp_ics_match_hwirq(wsp_ics, hw_irq))
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return -ENOENT;
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irq_set_chip_and_handler(virq, &wsp_irq_chip, handle_fasteoi_irq);
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irq_set_chip_data(virq, wsp_ics);
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spin_lock_irqsave(&wsp_ics->lock, flags);
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bitmap_allocate_region(wsp_ics->bitmap, hw_irq - wsp_ics->hwirq_start, 0);
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spin_unlock_irqrestore(&wsp_ics->lock, flags);
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return 0;
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}
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static void wsp_ics_mask_unknown(struct ics *ics, unsigned long hw_irq)
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{
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struct wsp_ics *wsp_ics = to_wsp_ics(ics);
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if (!wsp_ics_match_hwirq(wsp_ics, hw_irq))
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return;
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pr_err("%s: IRQ %lu (real) is invalid, disabling it.\n", __func__, hw_irq);
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wsp_mask_real_irq(hw_irq, wsp_ics);
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}
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static long wsp_ics_get_server(struct ics *ics, unsigned long hw_irq)
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{
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struct wsp_ics *wsp_ics = to_wsp_ics(ics);
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if (!wsp_ics_match_hwirq(wsp_ics, hw_irq))
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return -ENOENT;
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return get_irq_server(wsp_ics, hw_irq);
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}
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/* HW Number allocation API */
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static struct wsp_ics *wsp_ics_find_dn_ics(struct device_node *dn)
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{
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struct device_node *iparent;
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int i;
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iparent = of_irq_find_parent(dn);
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if (!iparent) {
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pr_err("wsp_ics: Failed to find interrupt parent!\n");
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return NULL;
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}
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for(i = 0; i < num_ics; i++) {
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if(ics_list[i].dn == iparent)
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break;
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}
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if (i >= num_ics) {
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pr_err("wsp_ics: Unable to find parent bitmap!\n");
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return NULL;
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}
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return &ics_list[i];
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}
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int wsp_ics_alloc_irq(struct device_node *dn, int num)
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{
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struct wsp_ics *ics;
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int order, offset;
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ics = wsp_ics_find_dn_ics(dn);
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if (!ics)
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return -ENODEV;
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/* Fast, but overly strict if num isn't a power of two */
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order = get_count_order(num);
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spin_lock_irq(&ics->lock);
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offset = bitmap_find_free_region(ics->bitmap, ics->count, order);
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spin_unlock_irq(&ics->lock);
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if (offset < 0)
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return offset;
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return offset + ics->hwirq_start;
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}
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void wsp_ics_free_irq(struct device_node *dn, unsigned int irq)
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{
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struct wsp_ics *ics;
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ics = wsp_ics_find_dn_ics(dn);
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if (WARN_ON(!ics))
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return;
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spin_lock_irq(&ics->lock);
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bitmap_release_region(ics->bitmap, irq, 0);
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spin_unlock_irq(&ics->lock);
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}
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/* Initialisation */
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static int __init wsp_ics_bitmap_setup(struct wsp_ics *ics,
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struct device_node *dn)
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{
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int len, i, j, size;
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u32 start, count;
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const u32 *p;
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size = BITS_TO_LONGS(ics->count) * sizeof(long);
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ics->bitmap = kzalloc(size, GFP_KERNEL);
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if (!ics->bitmap) {
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pr_err("wsp_ics: ENOMEM allocating IRQ bitmap!\n");
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return -ENOMEM;
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}
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spin_lock_init(&ics->lock);
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p = of_get_property(dn, "available-ranges", &len);
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if (!p || !len) {
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/* FIXME this should be a WARN() once mambo is updated */
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pr_err("wsp_ics: No available-ranges defined for %s\n",
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dn->full_name);
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return 0;
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}
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if (len % (2 * sizeof(u32)) != 0) {
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/* FIXME this should be a WARN() once mambo is updated */
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|
pr_err("wsp_ics: Invalid available-ranges for %s\n",
|
|
dn->full_name);
|
|
return 0;
|
|
}
|
|
|
|
bitmap_fill(ics->bitmap, ics->count);
|
|
|
|
for (i = 0; i < len / sizeof(u32); i += 2) {
|
|
start = of_read_number(p + i, 1);
|
|
count = of_read_number(p + i + 1, 1);
|
|
|
|
pr_devel("%s: start: %d count: %d\n", __func__, start, count);
|
|
|
|
if ((start + count) > (ics->hwirq_start + ics->count) ||
|
|
start < ics->hwirq_start) {
|
|
pr_err("wsp_ics: Invalid range! -> %d to %d\n",
|
|
start, start + count);
|
|
break;
|
|
}
|
|
|
|
for (j = 0; j < count; j++)
|
|
bitmap_release_region(ics->bitmap,
|
|
(start + j) - ics->hwirq_start, 0);
|
|
}
|
|
|
|
/* Ensure LSIs are not available for allocation */
|
|
bitmap_allocate_region(ics->bitmap, ics->lsi_base,
|
|
get_count_order(ics->lsi_count));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init wsp_ics_setup(struct wsp_ics *ics, struct device_node *dn)
|
|
{
|
|
u32 lsi_buid, msi_buid, msi_base, msi_count;
|
|
void __iomem *regs;
|
|
const u32 *p;
|
|
int rc, len, i;
|
|
u64 caps, buid;
|
|
|
|
p = of_get_property(dn, "interrupt-ranges", &len);
|
|
if (!p || len < (2 * sizeof(u32))) {
|
|
pr_err("wsp_ics: No/bad interrupt-ranges found on %s\n",
|
|
dn->full_name);
|
|
return -ENOENT;
|
|
}
|
|
|
|
if (len > (2 * sizeof(u32))) {
|
|
pr_err("wsp_ics: Multiple ics ranges not supported.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
regs = of_iomap(dn, 0);
|
|
if (!regs) {
|
|
pr_err("wsp_ics: of_iomap(%s) failed\n", dn->full_name);
|
|
return -ENXIO;
|
|
}
|
|
|
|
ics->hwirq_start = of_read_number(p, 1);
|
|
ics->count = of_read_number(p + 1, 1);
|
|
ics->regs = regs;
|
|
|
|
ics->chip_id = wsp_get_chip_id(dn);
|
|
if (WARN_ON(ics->chip_id < 0))
|
|
ics->chip_id = 0;
|
|
|
|
/* Get some informations about the critter */
|
|
caps = in_be64(ICS_INT_CAPS_REG(ics->regs));
|
|
buid = in_be64(INT_SRC_LAYER_BUID_REG(ics->regs));
|
|
ics->lsi_count = caps >> 56;
|
|
msi_count = (caps >> 44) & 0x7ff;
|
|
|
|
/* Note: LSI BUID is 9 bits, but really only 3 are BUID and the
|
|
* rest is mixed in the interrupt number. We store the whole
|
|
* thing though
|
|
*/
|
|
lsi_buid = (buid >> 48) & 0x1ff;
|
|
ics->lsi_base = (ics->chip_id << WSP_ICS_CHIP_SHIFT) | lsi_buid << 5;
|
|
msi_buid = (buid >> 37) & 0x7;
|
|
msi_base = (ics->chip_id << WSP_ICS_CHIP_SHIFT) | msi_buid << 11;
|
|
|
|
pr_info("wsp_ics: Found %s\n", dn->full_name);
|
|
pr_info("wsp_ics: irq range : 0x%06llx..0x%06llx\n",
|
|
ics->hwirq_start, ics->hwirq_start + ics->count - 1);
|
|
pr_info("wsp_ics: %4d LSIs : 0x%06x..0x%06x\n",
|
|
ics->lsi_count, ics->lsi_base,
|
|
ics->lsi_base + ics->lsi_count - 1);
|
|
pr_info("wsp_ics: %4d MSIs : 0x%06x..0x%06x\n",
|
|
msi_count, msi_base,
|
|
msi_base + msi_count - 1);
|
|
|
|
/* Let's check the HW config is sane */
|
|
if (ics->lsi_base < ics->hwirq_start ||
|
|
(ics->lsi_base + ics->lsi_count) > (ics->hwirq_start + ics->count))
|
|
pr_warning("wsp_ics: WARNING ! LSIs out of interrupt-ranges !\n");
|
|
if (msi_base < ics->hwirq_start ||
|
|
(msi_base + msi_count) > (ics->hwirq_start + ics->count))
|
|
pr_warning("wsp_ics: WARNING ! MSIs out of interrupt-ranges !\n");
|
|
|
|
/* We don't check for overlap between LSI and MSI, which will happen
|
|
* if we use the same BUID, I'm not sure yet how legit that is.
|
|
*/
|
|
|
|
rc = wsp_ics_bitmap_setup(ics, dn);
|
|
if (rc) {
|
|
iounmap(regs);
|
|
return rc;
|
|
}
|
|
|
|
ics->dn = of_node_get(dn);
|
|
alloc_irq_map(ics);
|
|
|
|
for(i = 0; i < ics->count; i++)
|
|
wsp_mask_real_irq(ics->hwirq_start + i, ics);
|
|
|
|
ics->ics.map = wsp_ics_map;
|
|
ics->ics.mask_unknown = wsp_ics_mask_unknown;
|
|
ics->ics.get_server = wsp_ics_get_server;
|
|
ics->ics.host_match = wsp_ics_host_match;
|
|
|
|
xics_register_ics(&ics->ics);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init wsp_ics_set_default_server(void)
|
|
{
|
|
struct device_node *np;
|
|
u32 hwid;
|
|
|
|
/* Find the server number for the boot cpu. */
|
|
np = of_get_cpu_node(boot_cpuid, NULL);
|
|
BUG_ON(!np);
|
|
|
|
hwid = get_hard_smp_processor_id(boot_cpuid);
|
|
|
|
pr_info("wsp_ics: default server is %#x, CPU %s\n", hwid, np->full_name);
|
|
xics_default_server = hwid;
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
static int __init wsp_ics_init(void)
|
|
{
|
|
struct device_node *dn;
|
|
struct wsp_ics *ics;
|
|
int rc, found;
|
|
|
|
wsp_ics_set_default_server();
|
|
|
|
found = 0;
|
|
for_each_compatible_node(dn, NULL, "ibm,ppc-xics")
|
|
found++;
|
|
|
|
if (found == 0) {
|
|
pr_err("wsp_ics: No ICS's found!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ics_list = kmalloc(sizeof(*ics) * found, GFP_KERNEL);
|
|
if (!ics_list) {
|
|
pr_err("wsp_ics: No memory for structs.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
num_ics = 0;
|
|
ics = ics_list;
|
|
for_each_compatible_node(dn, NULL, "ibm,wsp-xics") {
|
|
rc = wsp_ics_setup(ics, dn);
|
|
if (rc == 0) {
|
|
ics++;
|
|
num_ics++;
|
|
}
|
|
}
|
|
|
|
if (found != num_ics) {
|
|
pr_err("wsp_ics: Failed setting up %d ICS's\n",
|
|
found - num_ics);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init wsp_init_irq(void)
|
|
{
|
|
wsp_ics_init();
|
|
xics_init();
|
|
|
|
/* We need to patch our irq chip's EOI to point to the right ICP */
|
|
wsp_irq_chip.irq_eoi = icp_ops->eoi;
|
|
}
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
static void wsp_ics_msi_unmask_irq(struct irq_data *d)
|
|
{
|
|
wsp_chip_unmask_irq(d);
|
|
unmask_msi_irq(d);
|
|
}
|
|
|
|
static unsigned int wsp_ics_msi_startup(struct irq_data *d)
|
|
{
|
|
wsp_ics_msi_unmask_irq(d);
|
|
return 0;
|
|
}
|
|
|
|
static void wsp_ics_msi_mask_irq(struct irq_data *d)
|
|
{
|
|
mask_msi_irq(d);
|
|
wsp_chip_mask_irq(d);
|
|
}
|
|
|
|
/*
|
|
* we do it this way because we reassinge default EOI handling in
|
|
* irq_init() above
|
|
*/
|
|
static void wsp_ics_eoi(struct irq_data *data)
|
|
{
|
|
wsp_irq_chip.irq_eoi(data);
|
|
}
|
|
|
|
static struct irq_chip wsp_ics_msi = {
|
|
.name = "WSP ICS MSI",
|
|
.irq_startup = wsp_ics_msi_startup,
|
|
.irq_mask = wsp_ics_msi_mask_irq,
|
|
.irq_unmask = wsp_ics_msi_unmask_irq,
|
|
.irq_eoi = wsp_ics_eoi,
|
|
.irq_set_affinity = wsp_chip_set_affinity
|
|
};
|
|
|
|
void wsp_ics_set_msi_chip(unsigned int irq)
|
|
{
|
|
irq_set_chip(irq, &wsp_ics_msi);
|
|
}
|
|
|
|
void wsp_ics_set_std_chip(unsigned int irq)
|
|
{
|
|
irq_set_chip(irq, &wsp_irq_chip);
|
|
}
|
|
#endif /* CONFIG_PCI_MSI */
|