478 lines
9.9 KiB
C
478 lines
9.9 KiB
C
/**
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* @file nmi_int.c
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*
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* @remark Copyright 2002 OProfile authors
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* @remark Read the file COPYING
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*
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* @author John Levon <levon@movementarian.org>
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*/
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#include <linux/init.h>
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#include <linux/notifier.h>
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#include <linux/smp.h>
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#include <linux/oprofile.h>
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#include <linux/sysdev.h>
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#include <linux/slab.h>
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#include <linux/moduleparam.h>
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#include <linux/kdebug.h>
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#include <asm/nmi.h>
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#include <asm/msr.h>
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#include <asm/apic.h>
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#include "op_counter.h"
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#include "op_x86_model.h"
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static struct op_x86_model_spec const * model;
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static struct op_msrs cpu_msrs[NR_CPUS];
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static unsigned long saved_lvtpc[NR_CPUS];
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static int nmi_start(void);
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static void nmi_stop(void);
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/* 0 == registered but off, 1 == registered and on */
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static int nmi_enabled = 0;
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#ifdef CONFIG_PM
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static int nmi_suspend(struct sys_device *dev, pm_message_t state)
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{
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if (nmi_enabled == 1)
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nmi_stop();
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return 0;
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}
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static int nmi_resume(struct sys_device *dev)
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{
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if (nmi_enabled == 1)
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nmi_start();
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return 0;
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}
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static struct sysdev_class oprofile_sysclass = {
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.name = "oprofile",
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.resume = nmi_resume,
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.suspend = nmi_suspend,
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};
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static struct sys_device device_oprofile = {
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.id = 0,
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.cls = &oprofile_sysclass,
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};
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static int __init init_sysfs(void)
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{
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int error;
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if (!(error = sysdev_class_register(&oprofile_sysclass)))
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error = sysdev_register(&device_oprofile);
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return error;
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}
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static void exit_sysfs(void)
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{
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sysdev_unregister(&device_oprofile);
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sysdev_class_unregister(&oprofile_sysclass);
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}
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#else
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#define init_sysfs() do { } while (0)
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#define exit_sysfs() do { } while (0)
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#endif /* CONFIG_PM */
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static int profile_exceptions_notify(struct notifier_block *self,
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unsigned long val, void *data)
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{
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struct die_args *args = (struct die_args *)data;
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int ret = NOTIFY_DONE;
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int cpu = smp_processor_id();
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switch(val) {
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case DIE_NMI:
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if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
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ret = NOTIFY_STOP;
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break;
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default:
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break;
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}
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return ret;
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}
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static void nmi_cpu_save_registers(struct op_msrs * msrs)
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{
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unsigned int const nr_ctrs = model->num_counters;
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unsigned int const nr_ctrls = model->num_controls;
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struct op_msr * counters = msrs->counters;
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struct op_msr * controls = msrs->controls;
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unsigned int i;
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for (i = 0; i < nr_ctrs; ++i) {
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if (counters[i].addr){
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rdmsr(counters[i].addr,
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counters[i].saved.low,
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counters[i].saved.high);
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}
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}
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for (i = 0; i < nr_ctrls; ++i) {
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if (controls[i].addr){
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rdmsr(controls[i].addr,
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controls[i].saved.low,
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controls[i].saved.high);
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}
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}
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}
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static void nmi_save_registers(void * dummy)
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{
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int cpu = smp_processor_id();
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struct op_msrs * msrs = &cpu_msrs[cpu];
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nmi_cpu_save_registers(msrs);
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}
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static void free_msrs(void)
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{
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int i;
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for_each_possible_cpu(i) {
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kfree(cpu_msrs[i].counters);
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cpu_msrs[i].counters = NULL;
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kfree(cpu_msrs[i].controls);
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cpu_msrs[i].controls = NULL;
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}
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}
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static int allocate_msrs(void)
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{
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int success = 1;
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size_t controls_size = sizeof(struct op_msr) * model->num_controls;
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size_t counters_size = sizeof(struct op_msr) * model->num_counters;
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int i;
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for_each_possible_cpu(i) {
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cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
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if (!cpu_msrs[i].counters) {
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success = 0;
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break;
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}
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cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
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if (!cpu_msrs[i].controls) {
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success = 0;
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break;
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}
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}
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if (!success)
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free_msrs();
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return success;
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}
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static void nmi_cpu_setup(void * dummy)
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{
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int cpu = smp_processor_id();
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struct op_msrs * msrs = &cpu_msrs[cpu];
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spin_lock(&oprofilefs_lock);
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model->setup_ctrs(msrs);
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spin_unlock(&oprofilefs_lock);
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saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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}
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static struct notifier_block profile_exceptions_nb = {
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.notifier_call = profile_exceptions_notify,
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.next = NULL,
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.priority = 0
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};
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static int nmi_setup(void)
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{
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int err=0;
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int cpu;
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if (!allocate_msrs())
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return -ENOMEM;
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if ((err = register_die_notifier(&profile_exceptions_nb))){
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free_msrs();
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return err;
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}
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/* We need to serialize save and setup for HT because the subset
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* of msrs are distinct for save and setup operations
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*/
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/* Assume saved/restored counters are the same on all CPUs */
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model->fill_in_addresses(&cpu_msrs[0]);
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for_each_possible_cpu (cpu) {
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if (cpu != 0) {
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memcpy(cpu_msrs[cpu].counters, cpu_msrs[0].counters,
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sizeof(struct op_msr) * model->num_counters);
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memcpy(cpu_msrs[cpu].controls, cpu_msrs[0].controls,
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sizeof(struct op_msr) * model->num_controls);
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}
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}
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on_each_cpu(nmi_save_registers, NULL, 0, 1);
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on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
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nmi_enabled = 1;
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return 0;
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}
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static void nmi_restore_registers(struct op_msrs * msrs)
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{
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unsigned int const nr_ctrs = model->num_counters;
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unsigned int const nr_ctrls = model->num_controls;
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struct op_msr * counters = msrs->counters;
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struct op_msr * controls = msrs->controls;
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unsigned int i;
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for (i = 0; i < nr_ctrls; ++i) {
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if (controls[i].addr){
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wrmsr(controls[i].addr,
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controls[i].saved.low,
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controls[i].saved.high);
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}
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}
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for (i = 0; i < nr_ctrs; ++i) {
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if (counters[i].addr){
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wrmsr(counters[i].addr,
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counters[i].saved.low,
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counters[i].saved.high);
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}
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}
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}
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static void nmi_cpu_shutdown(void * dummy)
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{
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unsigned int v;
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int cpu = smp_processor_id();
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struct op_msrs * msrs = &cpu_msrs[cpu];
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/* restoring APIC_LVTPC can trigger an apic error because the delivery
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* mode and vector nr combination can be illegal. That's by design: on
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* power on apic lvt contain a zero vector nr which are legal only for
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* NMI delivery mode. So inhibit apic err before restoring lvtpc
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*/
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v = apic_read(APIC_LVTERR);
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apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
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apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
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apic_write(APIC_LVTERR, v);
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nmi_restore_registers(msrs);
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}
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static void nmi_shutdown(void)
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{
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nmi_enabled = 0;
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on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
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unregister_die_notifier(&profile_exceptions_nb);
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model->shutdown(cpu_msrs);
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free_msrs();
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}
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static void nmi_cpu_start(void * dummy)
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{
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struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
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model->start(msrs);
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}
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static int nmi_start(void)
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{
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on_each_cpu(nmi_cpu_start, NULL, 0, 1);
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return 0;
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}
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static void nmi_cpu_stop(void * dummy)
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{
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struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
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model->stop(msrs);
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}
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static void nmi_stop(void)
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{
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on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
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}
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struct op_counter_config counter_config[OP_MAX_COUNTER];
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static int nmi_create_files(struct super_block * sb, struct dentry * root)
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{
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unsigned int i;
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for (i = 0; i < model->num_counters; ++i) {
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struct dentry * dir;
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char buf[4];
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/* quick little hack to _not_ expose a counter if it is not
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* available for use. This should protect userspace app.
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* NOTE: assumes 1:1 mapping here (that counters are organized
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* sequentially in their struct assignment).
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*/
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if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
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continue;
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snprintf(buf, sizeof(buf), "%d", i);
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dir = oprofilefs_mkdir(sb, root, buf);
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oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
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oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
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oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
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oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
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oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
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oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
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}
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return 0;
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}
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static int p4force;
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module_param(p4force, int, 0);
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static int __init p4_init(char ** cpu_type)
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{
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__u8 cpu_model = boot_cpu_data.x86_model;
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if (!p4force && (cpu_model > 6 || cpu_model == 5))
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return 0;
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#ifndef CONFIG_SMP
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*cpu_type = "i386/p4";
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model = &op_p4_spec;
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return 1;
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#else
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switch (smp_num_siblings) {
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case 1:
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*cpu_type = "i386/p4";
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model = &op_p4_spec;
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return 1;
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case 2:
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*cpu_type = "i386/p4-ht";
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model = &op_p4_ht2_spec;
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return 1;
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}
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#endif
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printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
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printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
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return 0;
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}
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static int __init ppro_init(char ** cpu_type)
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{
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__u8 cpu_model = boot_cpu_data.x86_model;
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if (cpu_model == 14)
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*cpu_type = "i386/core";
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else if (cpu_model == 15 || cpu_model == 23)
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*cpu_type = "i386/core_2";
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else if (cpu_model > 0xd)
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return 0;
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else if (cpu_model == 9) {
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*cpu_type = "i386/p6_mobile";
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} else if (cpu_model > 5) {
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*cpu_type = "i386/piii";
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} else if (cpu_model > 2) {
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*cpu_type = "i386/pii";
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} else {
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*cpu_type = "i386/ppro";
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}
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model = &op_ppro_spec;
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return 1;
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}
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/* in order to get sysfs right */
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static int using_nmi;
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int __init op_nmi_init(struct oprofile_operations *ops)
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{
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__u8 vendor = boot_cpu_data.x86_vendor;
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__u8 family = boot_cpu_data.x86;
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char *cpu_type;
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if (!cpu_has_apic)
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return -ENODEV;
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switch (vendor) {
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case X86_VENDOR_AMD:
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/* Needs to be at least an Athlon (or hammer in 32bit mode) */
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switch (family) {
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default:
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return -ENODEV;
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case 6:
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model = &op_athlon_spec;
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cpu_type = "i386/athlon";
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break;
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case 0xf:
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model = &op_athlon_spec;
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/* Actually it could be i386/hammer too, but give
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user space an consistent name. */
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cpu_type = "x86-64/hammer";
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break;
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case 0x10:
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model = &op_athlon_spec;
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cpu_type = "x86-64/family10";
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break;
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}
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break;
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case X86_VENDOR_INTEL:
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switch (family) {
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/* Pentium IV */
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case 0xf:
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if (!p4_init(&cpu_type))
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return -ENODEV;
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break;
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/* A P6-class processor */
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case 6:
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if (!ppro_init(&cpu_type))
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return -ENODEV;
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break;
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default:
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return -ENODEV;
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}
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break;
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default:
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return -ENODEV;
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}
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init_sysfs();
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using_nmi = 1;
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ops->create_files = nmi_create_files;
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ops->setup = nmi_setup;
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ops->shutdown = nmi_shutdown;
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ops->start = nmi_start;
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ops->stop = nmi_stop;
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ops->cpu_type = cpu_type;
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printk(KERN_INFO "oprofile: using NMI interrupt.\n");
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return 0;
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}
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void op_nmi_exit(void)
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{
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if (using_nmi)
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exit_sysfs();
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}
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