252 lines
8.5 KiB
C
252 lines
8.5 KiB
C
/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright (C) 2012 Intel Corporation
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* Author: Yuanhan Liu <yuanhan.liu@linux.intel.com>
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*
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* Based on sse2.c: Copyright 2002 H. Peter Anvin - All Rights Reserved
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Boston MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* ----------------------------------------------------------------------- */
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/*
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* AVX2 implementation of RAID-6 syndrome functions
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*
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*/
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#ifdef CONFIG_AS_AVX2
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#include <linux/raid/pq.h>
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#include "x86.h"
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static const struct raid6_avx2_constants {
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u64 x1d[4];
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} raid6_avx2_constants __aligned(32) = {
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{ 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,
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0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,},
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};
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static int raid6_have_avx2(void)
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{
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return boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX);
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}
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/*
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* Plain AVX2 implementation
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*/
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static void raid6_avx21_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
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asm volatile("vpxor %ymm3,%ymm3,%ymm3"); /* Zero temp */
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for (d = 0; d < bytes; d += 32) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
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asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
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asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d]));
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asm volatile("vmovdqa %ymm2,%ymm4");/* Q[0] */
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asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z0-1][d]));
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for (z = z0-2; z >= 0; z--) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
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asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm6,%ymm2,%ymm2");
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asm volatile("vpxor %ymm6,%ymm4,%ymm4");
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asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z][d]));
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}
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asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm6,%ymm2,%ymm2");
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asm volatile("vpxor %ymm6,%ymm4,%ymm4");
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asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
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asm volatile("vpxor %ymm2,%ymm2,%ymm2");
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asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
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asm volatile("vpxor %ymm4,%ymm4,%ymm4");
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx2x1 = {
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raid6_avx21_gen_syndrome,
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raid6_have_avx2,
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"avx2x1",
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1 /* Has cache hints */
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};
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/*
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* Unrolled-by-2 AVX2 implementation
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*/
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static void raid6_avx22_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
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asm volatile("vpxor %ymm1,%ymm1,%ymm1"); /* Zero temp */
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/* We uniformly assume a single prefetch covers at least 32 bytes */
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for (d = 0; d < bytes; d += 64) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d+32]));
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asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
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asm volatile("vmovdqa %0,%%ymm3" : : "m" (dptr[z0][d+32]));/* P[1] */
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asm volatile("vmovdqa %ymm2,%ymm4"); /* Q[0] */
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asm volatile("vmovdqa %ymm3,%ymm6"); /* Q[1] */
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for (z = z0-1; z >= 0; z--) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
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asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
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asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpand %ymm0,%ymm7,%ymm7");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
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asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
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asm volatile("vpxor %ymm5,%ymm2,%ymm2");
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asm volatile("vpxor %ymm7,%ymm3,%ymm3");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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}
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asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
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asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
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asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
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asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx2x2 = {
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raid6_avx22_gen_syndrome,
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raid6_have_avx2,
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"avx2x2",
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1 /* Has cache hints */
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};
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#ifdef CONFIG_X86_64
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/*
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* Unrolled-by-4 AVX2 implementation
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*/
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static void raid6_avx24_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
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asm volatile("vpxor %ymm1,%ymm1,%ymm1"); /* Zero temp */
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asm volatile("vpxor %ymm2,%ymm2,%ymm2"); /* P[0] */
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asm volatile("vpxor %ymm3,%ymm3,%ymm3"); /* P[1] */
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asm volatile("vpxor %ymm4,%ymm4,%ymm4"); /* Q[0] */
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asm volatile("vpxor %ymm6,%ymm6,%ymm6"); /* Q[1] */
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asm volatile("vpxor %ymm10,%ymm10,%ymm10"); /* P[2] */
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asm volatile("vpxor %ymm11,%ymm11,%ymm11"); /* P[3] */
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asm volatile("vpxor %ymm12,%ymm12,%ymm12"); /* Q[2] */
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asm volatile("vpxor %ymm14,%ymm14,%ymm14"); /* Q[3] */
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for (d = 0; d < bytes; d += 128) {
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for (z = z0; z >= 0; z--) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d+64]));
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d+96]));
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asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
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asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
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asm volatile("vpcmpgtb %ymm12,%ymm1,%ymm13");
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asm volatile("vpcmpgtb %ymm14,%ymm1,%ymm15");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
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asm volatile("vpaddb %ymm12,%ymm12,%ymm12");
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asm volatile("vpaddb %ymm14,%ymm14,%ymm14");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpand %ymm0,%ymm7,%ymm7");
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asm volatile("vpand %ymm0,%ymm13,%ymm13");
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asm volatile("vpand %ymm0,%ymm15,%ymm15");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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asm volatile("vpxor %ymm13,%ymm12,%ymm12");
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asm volatile("vpxor %ymm15,%ymm14,%ymm14");
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asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
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asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
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asm volatile("vmovdqa %0,%%ymm13" : : "m" (dptr[z][d+64]));
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asm volatile("vmovdqa %0,%%ymm15" : : "m" (dptr[z][d+96]));
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asm volatile("vpxor %ymm5,%ymm2,%ymm2");
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asm volatile("vpxor %ymm7,%ymm3,%ymm3");
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asm volatile("vpxor %ymm13,%ymm10,%ymm10");
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asm volatile("vpxor %ymm15,%ymm11,%ymm11");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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asm volatile("vpxor %ymm13,%ymm12,%ymm12");
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asm volatile("vpxor %ymm15,%ymm14,%ymm14");
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}
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asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
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asm volatile("vpxor %ymm2,%ymm2,%ymm2");
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asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
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asm volatile("vpxor %ymm3,%ymm3,%ymm3");
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asm volatile("vmovntdq %%ymm10,%0" : "=m" (p[d+64]));
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asm volatile("vpxor %ymm10,%ymm10,%ymm10");
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asm volatile("vmovntdq %%ymm11,%0" : "=m" (p[d+96]));
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asm volatile("vpxor %ymm11,%ymm11,%ymm11");
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asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
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asm volatile("vpxor %ymm4,%ymm4,%ymm4");
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asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
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asm volatile("vpxor %ymm6,%ymm6,%ymm6");
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asm volatile("vmovntdq %%ymm12,%0" : "=m" (q[d+64]));
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asm volatile("vpxor %ymm12,%ymm12,%ymm12");
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asm volatile("vmovntdq %%ymm14,%0" : "=m" (q[d+96]));
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asm volatile("vpxor %ymm14,%ymm14,%ymm14");
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx2x4 = {
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raid6_avx24_gen_syndrome,
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raid6_have_avx2,
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"avx2x4",
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1 /* Has cache hints */
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};
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#endif
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#endif /* CONFIG_AS_AVX2 */
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