182 lines
3.2 KiB
C
182 lines
3.2 KiB
C
/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <asm/clock.h>
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#include <asm/time.h>
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#include <loongson1.h>
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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struct clk *clk_get(struct device *dev, const char *name)
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{
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struct clk *c;
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struct clk *ret = NULL;
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mutex_lock(&clocks_mutex);
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list_for_each_entry(c, &clocks, node) {
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if (!strcmp(c->name, name)) {
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ret = c;
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break;
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}
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}
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mutex_unlock(&clocks_mutex);
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return ret;
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}
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EXPORT_SYMBOL(clk_get);
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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static void pll_clk_init(struct clk *clk)
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{
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u32 pll;
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pll = __raw_readl(LS1X_CLK_PLL_FREQ);
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clk->rate = (12 + (pll & 0x3f)) * 33 / 2
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+ ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
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clk->rate *= 1000000;
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}
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static void cpu_clk_init(struct clk *clk)
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{
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u32 pll, ctrl;
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pll = clk_get_rate(clk->parent);
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ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
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clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
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}
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static void ddr_clk_init(struct clk *clk)
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{
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u32 pll, ctrl;
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pll = clk_get_rate(clk->parent);
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ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
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clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
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}
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static void dc_clk_init(struct clk *clk)
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{
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u32 pll, ctrl;
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pll = clk_get_rate(clk->parent);
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ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
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clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
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}
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static struct clk_ops pll_clk_ops = {
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.init = pll_clk_init,
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};
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static struct clk_ops cpu_clk_ops = {
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.init = cpu_clk_init,
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};
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static struct clk_ops ddr_clk_ops = {
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.init = ddr_clk_init,
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};
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static struct clk_ops dc_clk_ops = {
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.init = dc_clk_init,
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};
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static struct clk pll_clk = {
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.name = "pll",
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.ops = &pll_clk_ops,
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};
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static struct clk cpu_clk = {
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.name = "cpu",
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.parent = &pll_clk,
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.ops = &cpu_clk_ops,
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};
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static struct clk ddr_clk = {
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.name = "ddr",
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.parent = &pll_clk,
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.ops = &ddr_clk_ops,
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};
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static struct clk dc_clk = {
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.name = "dc",
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.parent = &pll_clk,
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.ops = &dc_clk_ops,
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};
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int clk_register(struct clk *clk)
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{
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mutex_lock(&clocks_mutex);
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list_add(&clk->node, &clocks);
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if (clk->ops->init)
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clk->ops->init(clk);
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mutex_unlock(&clocks_mutex);
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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static struct clk *ls1x_clks[] = {
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&pll_clk,
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&cpu_clk,
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&ddr_clk,
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&dc_clk,
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};
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int __init ls1x_clock_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++)
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clk_register(ls1x_clks[i]);
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return 0;
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}
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void __init plat_time_init(void)
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{
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struct clk *clk;
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/* Initialize LS1X clocks */
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ls1x_clock_init();
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/* setup mips r4k timer */
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clk = clk_get(NULL, "cpu");
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if (IS_ERR(clk))
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panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
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mips_hpt_frequency = clk_get_rate(clk) / 2;
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}
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