502 lines
12 KiB
C
502 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/system.h>
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extern void build_tlb_refill_handler(void);
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/*
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* Make sure all entries differ. If they're not different
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* MIPS32 will take revenge ...
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*/
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#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
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/* Atomicity and interruptability */
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/smtc.h>
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#include <asm/mipsmtregs.h>
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#define ENTER_CRITICAL(flags) \
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{ \
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unsigned int mvpflags; \
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local_irq_save(flags);\
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mvpflags = dvpe()
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#define EXIT_CRITICAL(flags) \
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evpe(mvpflags); \
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local_irq_restore(flags); \
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}
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#else
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#define ENTER_CRITICAL(flags) local_irq_save(flags)
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#define EXIT_CRITICAL(flags) local_irq_restore(flags)
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#endif /* CONFIG_MIPS_MT_SMTC */
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#if defined(CONFIG_CPU_LOONGSON2)
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/*
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* LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
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* unfortrunately, itlb is not totally transparent to software.
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*/
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#define FLUSH_ITLB write_c0_diag(4);
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#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
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#else
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#define FLUSH_ITLB
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#define FLUSH_ITLB_VM(vma)
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#endif
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void local_flush_tlb_all(void)
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{
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unsigned long flags;
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unsigned long old_ctx;
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int entry;
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ENTER_CRITICAL(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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entry = read_c0_wired();
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/* Blast 'em all away. */
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while (entry < current_cpu_data.tlbsize) {
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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write_c0_index(entry);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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entry++;
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}
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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FLUSH_ITLB;
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EXIT_CRITICAL(flags);
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}
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/* All entries common to a mm share an asid. To effectively flush
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these entries, we just bump the asid. */
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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int cpu;
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preempt_disable();
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cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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drop_mmu_context(mm, cpu);
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}
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preempt_enable();
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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unsigned long size, flags;
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ENTER_CRITICAL(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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if (size <= current_cpu_data.tlbsize/2) {
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int oldpid = read_c0_entryhi();
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int newpid = cpu_asid(cpu, mm);
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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while (start < end) {
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int idx;
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write_c0_entryhi(start | newpid);
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start += (PAGE_SIZE << 1);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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if (idx < 0)
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continue;
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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}
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tlbw_use_hazard();
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write_c0_entryhi(oldpid);
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} else {
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drop_mmu_context(mm, cpu);
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}
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FLUSH_ITLB;
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EXIT_CRITICAL(flags);
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}
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long size, flags;
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ENTER_CRITICAL(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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if (size <= current_cpu_data.tlbsize / 2) {
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int pid = read_c0_entryhi();
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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while (start < end) {
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int idx;
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write_c0_entryhi(start);
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start += (PAGE_SIZE << 1);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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if (idx < 0)
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continue;
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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}
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tlbw_use_hazard();
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write_c0_entryhi(pid);
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} else {
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local_flush_tlb_all();
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}
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FLUSH_ITLB;
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EXIT_CRITICAL(flags);
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}
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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int cpu = smp_processor_id();
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if (cpu_context(cpu, vma->vm_mm) != 0) {
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unsigned long flags;
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int oldpid, newpid, idx;
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newpid = cpu_asid(cpu, vma->vm_mm);
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page &= (PAGE_MASK << 1);
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ENTER_CRITICAL(flags);
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oldpid = read_c0_entryhi();
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write_c0_entryhi(page | newpid);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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if (idx < 0)
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goto finish;
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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finish:
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write_c0_entryhi(oldpid);
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FLUSH_ITLB_VM(vma);
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EXIT_CRITICAL(flags);
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}
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}
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/*
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* This one is only used for pages with the global bit set so we don't care
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* much about the ASID.
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*/
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void local_flush_tlb_one(unsigned long page)
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{
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unsigned long flags;
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int oldpid, idx;
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ENTER_CRITICAL(flags);
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oldpid = read_c0_entryhi();
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page &= (PAGE_MASK << 1);
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write_c0_entryhi(page);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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if (idx >= 0) {
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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}
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write_c0_entryhi(oldpid);
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FLUSH_ITLB;
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EXIT_CRITICAL(flags);
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}
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/*
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* We will need multiple versions of update_mmu_cache(), one that just
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* updates the TLB with the new pte(s), and another which also checks
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* for the R4k "end of page" hardware bug and does the needy.
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*/
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void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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{
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unsigned long flags;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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int idx, pid;
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/*
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* Handle debugger faulting in for debugee.
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*/
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if (current->active_mm != vma->vm_mm)
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return;
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ENTER_CRITICAL(flags);
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pid = read_c0_entryhi() & ASID_MASK;
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address &= (PAGE_MASK << 1);
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write_c0_entryhi(address | pid);
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pgdp = pgd_offset(vma->vm_mm, address);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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pudp = pud_offset(pgdp, address);
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pmdp = pmd_offset(pudp, address);
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idx = read_c0_index();
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ptep = pte_offset_map(pmdp, address);
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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write_c0_entrylo0(ptep->pte_high);
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ptep++;
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write_c0_entrylo1(ptep->pte_high);
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#else
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write_c0_entrylo0(pte_val(*ptep++) >> 6);
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write_c0_entrylo1(pte_val(*ptep) >> 6);
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#endif
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mtc0_tlbw_hazard();
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if (idx < 0)
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tlb_write_random();
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else
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tlb_write_indexed();
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tlbw_use_hazard();
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FLUSH_ITLB_VM(vma);
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EXIT_CRITICAL(flags);
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}
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#if 0
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static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
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unsigned long address, pte_t pte)
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{
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unsigned long flags;
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unsigned int asid;
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pgd_t *pgdp;
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pmd_t *pmdp;
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pte_t *ptep;
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int idx;
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ENTER_CRITICAL(flags);
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address &= (PAGE_MASK << 1);
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asid = read_c0_entryhi() & ASID_MASK;
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write_c0_entryhi(address | asid);
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pgdp = pgd_offset(vma->vm_mm, address);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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pmdp = pmd_offset(pgdp, address);
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idx = read_c0_index();
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ptep = pte_offset_map(pmdp, address);
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write_c0_entrylo0(pte_val(*ptep++) >> 6);
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write_c0_entrylo1(pte_val(*ptep) >> 6);
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mtc0_tlbw_hazard();
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if (idx < 0)
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tlb_write_random();
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else
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tlb_write_indexed();
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tlbw_use_hazard();
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EXIT_CRITICAL(flags);
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}
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#endif
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void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask)
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{
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unsigned long flags;
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unsigned long wired;
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unsigned long old_pagemask;
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unsigned long old_ctx;
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ENTER_CRITICAL(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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old_pagemask = read_c0_pagemask();
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wired = read_c0_wired();
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write_c0_wired(wired + 1);
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write_c0_index(wired);
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tlbw_use_hazard(); /* What is the hazard here? */
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write_c0_pagemask(pagemask);
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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write_c0_entrylo1(entrylo1);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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tlbw_use_hazard(); /* What is the hazard here? */
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write_c0_pagemask(old_pagemask);
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local_flush_tlb_all();
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EXIT_CRITICAL(flags);
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}
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/*
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* Used for loading TLB entries before trap_init() has started, when we
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* don't actually want to add a wired entry which remains throughout the
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* lifetime of the system
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*/
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static int temp_tlb_entry __cpuinitdata;
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__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask)
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{
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int ret = 0;
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unsigned long flags;
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unsigned long wired;
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unsigned long old_pagemask;
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unsigned long old_ctx;
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ENTER_CRITICAL(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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old_pagemask = read_c0_pagemask();
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wired = read_c0_wired();
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if (--temp_tlb_entry < wired) {
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printk(KERN_WARNING
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"No TLB space left for add_temporary_entry\n");
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ret = -ENOSPC;
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goto out;
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}
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write_c0_index(temp_tlb_entry);
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write_c0_pagemask(pagemask);
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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write_c0_entrylo1(entrylo1);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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write_c0_pagemask(old_pagemask);
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out:
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EXIT_CRITICAL(flags);
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return ret;
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}
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static void __cpuinit probe_tlb(unsigned long config)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int reg;
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/*
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* If this isn't a MIPS32 / MIPS64 compliant CPU. Config 1 register
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* is not supported, we assume R4k style. Cpu probing already figured
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* out the number of tlb entries.
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*/
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if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
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return;
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* If TLB is shared in SMTC system, total size already
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* has been calculated and written into cpu_data tlbsize
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*/
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if((smtc_status & SMTC_TLB_SHARED) == SMTC_TLB_SHARED)
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return;
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#endif /* CONFIG_MIPS_MT_SMTC */
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reg = read_c0_config1();
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if (!((config >> 7) & 3))
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panic("No TLB present");
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c->tlbsize = ((reg >> 25) & 0x3f) + 1;
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}
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static int __cpuinitdata ntlb = 0;
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static int __init set_ntlb(char *str)
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{
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get_option(&str, &ntlb);
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return 1;
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}
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__setup("ntlb=", set_ntlb);
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void __cpuinit tlb_init(void)
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{
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unsigned int config = read_c0_config();
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/*
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* You should never change this register:
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* - On R4600 1.7 the tlbp never hits for pages smaller than
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* the value in the c0_pagemask register.
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* - The entire mm handling assumes the c0_pagemask register to
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* be set to fixed-size pages.
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*/
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probe_tlb(config);
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write_c0_pagemask(PM_DEFAULT_MASK);
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write_c0_wired(0);
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if (current_cpu_type() == CPU_R10000 ||
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current_cpu_type() == CPU_R12000 ||
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current_cpu_type() == CPU_R14000)
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write_c0_framemask(0);
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temp_tlb_entry = current_cpu_data.tlbsize - 1;
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/* From this point on the ARC firmware is dead. */
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local_flush_tlb_all();
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/* Did I tell you that ARC SUCKS? */
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if (ntlb) {
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if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
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int wired = current_cpu_data.tlbsize - ntlb;
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write_c0_wired(wired);
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write_c0_index(wired-1);
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printk("Restricting TLB to %d entries\n", ntlb);
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} else
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printk("Ignoring invalid argument ntlb=%d\n", ntlb);
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}
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build_tlb_refill_handler();
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}
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