408 lines
10 KiB
C
408 lines
10 KiB
C
/*
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* Copyright (C) 2009 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/plat-ram.h>
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#include <linux/memory.h>
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#include <linux/gpio.h>
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#include <linux/smc911x.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/i2c/at24.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/ulpi.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "devices-imx35.h"
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#include "hardware.h"
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#include "iomux-mx35.h"
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#include "ulpi.h"
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static const struct fb_videomode fb_modedb[] = {
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{
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/* 240x320 @ 60 Hz */
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.name = "Sharp-LQ035Q7",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 185925,
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.left_margin = 9,
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.right_margin = 16,
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.upper_margin = 7,
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.lower_margin = 9,
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.hsync_len = 1,
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.vsync_len = 1,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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}, {
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/* 240x320 @ 60 Hz */
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.name = "TX090",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 38255,
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.left_margin = 144,
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.right_margin = 0,
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.upper_margin = 7,
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.lower_margin = 40,
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.hsync_len = 96,
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.vsync_len = 1,
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.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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},
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};
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static struct mx3fb_platform_data mx3fb_pdata __initdata = {
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.name = "Sharp-LQ035Q7",
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.mode = fb_modedb,
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.num_modes = ARRAY_SIZE(fb_modedb),
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};
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static struct physmap_flash_data pcm043_flash_data = {
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.width = 2,
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};
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static struct resource pcm043_flash_resource = {
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.start = 0xa0000000,
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.end = 0xa1ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device pcm043_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &pcm043_flash_data,
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},
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.resource = &pcm043_flash_resource,
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.num_resources = 1,
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};
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
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.bitrate = 50000,
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};
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static struct at24_platform_data board_eeprom = {
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.byte_len = 4096,
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.page_size = 32,
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.flags = AT24_FLAG_ADDR16,
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};
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static struct i2c_board_info pcm043_i2c_devices[] = {
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{
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I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
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.platform_data = &board_eeprom,
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}, {
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I2C_BOARD_INFO("pcf8563", 0x51),
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},
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};
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static struct platform_device *devices[] __initdata = {
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&pcm043_flash,
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};
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static iomux_v3_cfg_t pcm043_pads[] = {
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/* UART1 */
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MX35_PAD_CTS1__UART1_CTS,
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MX35_PAD_RTS1__UART1_RTS,
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MX35_PAD_TXD1__UART1_TXD_MUX,
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MX35_PAD_RXD1__UART1_RXD_MUX,
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/* UART2 */
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MX35_PAD_CTS2__UART2_CTS,
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MX35_PAD_RTS2__UART2_RTS,
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MX35_PAD_TXD2__UART2_TXD_MUX,
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MX35_PAD_RXD2__UART2_RXD_MUX,
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/* FEC */
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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/* I2C1 */
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MX35_PAD_I2C1_CLK__I2C1_SCL,
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MX35_PAD_I2C1_DAT__I2C1_SDA,
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/* Display */
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MX35_PAD_LD0__IPU_DISPB_DAT_0,
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MX35_PAD_LD1__IPU_DISPB_DAT_1,
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MX35_PAD_LD2__IPU_DISPB_DAT_2,
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MX35_PAD_LD3__IPU_DISPB_DAT_3,
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MX35_PAD_LD4__IPU_DISPB_DAT_4,
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MX35_PAD_LD5__IPU_DISPB_DAT_5,
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MX35_PAD_LD6__IPU_DISPB_DAT_6,
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MX35_PAD_LD7__IPU_DISPB_DAT_7,
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MX35_PAD_LD8__IPU_DISPB_DAT_8,
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MX35_PAD_LD9__IPU_DISPB_DAT_9,
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MX35_PAD_LD10__IPU_DISPB_DAT_10,
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MX35_PAD_LD11__IPU_DISPB_DAT_11,
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MX35_PAD_LD12__IPU_DISPB_DAT_12,
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MX35_PAD_LD13__IPU_DISPB_DAT_13,
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MX35_PAD_LD14__IPU_DISPB_DAT_14,
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MX35_PAD_LD15__IPU_DISPB_DAT_15,
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MX35_PAD_LD16__IPU_DISPB_DAT_16,
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MX35_PAD_LD17__IPU_DISPB_DAT_17,
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MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
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MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
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MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
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MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
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MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
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MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
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MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
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/* gpio */
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MX35_PAD_ATA_CS0__GPIO2_6,
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/* USB host */
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MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
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MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
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/* SSI */
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MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
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MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
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MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
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MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
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/* CAN2 */
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MX35_PAD_TX5_RX0__CAN2_TXCAN,
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MX35_PAD_TX4_RX1__CAN2_RXCAN,
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/* esdhc */
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MX35_PAD_SD1_CMD__ESDHC1_CMD,
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MX35_PAD_SD1_CLK__ESDHC1_CLK,
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MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
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MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
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MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
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MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
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MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
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MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
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};
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#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
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#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
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#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
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#define SD1_GPIO_WP IMX_GPIO_NR(2, 23)
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#define SD1_GPIO_CD IMX_GPIO_NR(2, 24)
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static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
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iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
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int ret;
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ret = gpio_request(AC97_GPIO_TXFS, "SSI");
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if (ret) {
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printk("failed to get GPIO_TXFS: %d\n", ret);
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return;
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}
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mxc_iomux_v3_setup_pad(txfs_gpio);
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/* warm reset */
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gpio_direction_output(AC97_GPIO_TXFS, 1);
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udelay(2);
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gpio_set_value(AC97_GPIO_TXFS, 0);
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gpio_free(AC97_GPIO_TXFS);
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mxc_iomux_v3_setup_pad(txfs);
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}
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static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
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iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
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iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
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iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
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iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
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int ret;
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ret = gpio_request(AC97_GPIO_TXFS, "SSI");
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if (ret)
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goto err1;
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ret = gpio_request(AC97_GPIO_TXD, "SSI");
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if (ret)
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goto err2;
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ret = gpio_request(AC97_GPIO_RESET, "SSI");
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if (ret)
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goto err3;
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mxc_iomux_v3_setup_pad(txfs_gpio);
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mxc_iomux_v3_setup_pad(txd_gpio);
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mxc_iomux_v3_setup_pad(reset_gpio);
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gpio_direction_output(AC97_GPIO_TXFS, 0);
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gpio_direction_output(AC97_GPIO_TXD, 0);
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/* cold reset */
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gpio_direction_output(AC97_GPIO_RESET, 0);
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udelay(10);
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gpio_direction_output(AC97_GPIO_RESET, 1);
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mxc_iomux_v3_setup_pad(txd);
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mxc_iomux_v3_setup_pad(txfs);
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gpio_free(AC97_GPIO_RESET);
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err3:
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gpio_free(AC97_GPIO_TXD);
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err2:
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gpio_free(AC97_GPIO_TXFS);
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err1:
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if (ret)
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printk("%s failed with %d\n", __func__, ret);
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mdelay(1);
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}
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static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
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.ac97_reset = pcm043_ac97_cold_reset,
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.ac97_warm_reset = pcm043_ac97_warm_reset,
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.flags = IMX_SSI_USE_AC97,
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};
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static const struct mxc_nand_platform_data
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pcm037_nand_board_info __initconst = {
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.width = 1,
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.hw_ecc = 1,
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};
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static int pcm043_otg_init(struct platform_device *pdev)
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{
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return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
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}
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static struct mxc_usbh_platform_data otg_pdata __initdata = {
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.init = pcm043_otg_init,
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.portsc = MXC_EHCI_MODE_UTMI,
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};
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static int pcm043_usbh1_init(struct platform_device *pdev)
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{
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return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
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MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
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}
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static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
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.init = pcm043_usbh1_init,
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.portsc = MXC_EHCI_MODE_SERIAL,
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};
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static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
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.operating_mode = FSL_USB2_DR_DEVICE,
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.phy_mode = FSL_USB2_PHY_UTMI,
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};
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static bool otg_mode_host __initdata;
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static int __init pcm043_otg_mode(char *options)
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{
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if (!strcmp(options, "host"))
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otg_mode_host = true;
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else if (!strcmp(options, "device"))
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otg_mode_host = false;
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else
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pr_info("otg_mode neither \"host\" nor \"device\". "
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"Defaulting to device\n");
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return 1;
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}
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__setup("otg_mode=", pcm043_otg_mode);
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static struct esdhc_platform_data sd1_pdata = {
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.wp_gpio = SD1_GPIO_WP,
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.cd_gpio = SD1_GPIO_CD,
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.wp_type = ESDHC_WP_GPIO,
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.cd_type = ESDHC_CD_GPIO,
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};
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/*
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* Board specific initialization.
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*/
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static void __init pcm043_init(void)
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{
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imx35_soc_init();
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mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
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imx35_add_fec(NULL);
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platform_add_devices(devices, ARRAY_SIZE(devices));
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imx35_add_imx2_wdt();
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imx35_add_imx_uart0(&uart_pdata);
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imx35_add_mxc_nand(&pcm037_nand_board_info);
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imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
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imx35_add_imx_uart1(&uart_pdata);
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i2c_register_board_info(0, pcm043_i2c_devices,
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ARRAY_SIZE(pcm043_i2c_devices));
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imx35_add_imx_i2c0(&pcm043_i2c0_data);
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imx35_add_ipu_core();
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imx35_add_mx3_sdc_fb(&mx3fb_pdata);
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if (otg_mode_host) {
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otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
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ULPI_OTG_DRVVBUS_EXT);
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if (otg_pdata.otg)
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imx35_add_mxc_ehci_otg(&otg_pdata);
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}
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imx35_add_mxc_ehci_hs(&usbh1_pdata);
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if (!otg_mode_host)
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imx35_add_fsl_usb2_udc(&otg_device_pdata);
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imx35_add_flexcan1();
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imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
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}
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static void __init pcm043_timer_init(void)
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{
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mx35_clocks_init();
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}
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MACHINE_START(PCM043, "Phytec Phycore pcm043")
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/* Maintainer: Pengutronix */
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.atag_offset = 0x100,
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.map_io = mx35_map_io,
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.init_early = imx35_init_early,
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.init_irq = mx35_init_irq,
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.handle_irq = imx35_handle_irq,
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.init_time = pcm043_timer_init,
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.init_machine = pcm043_init,
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.restart = mxc_restart,
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MACHINE_END
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