1725 lines
43 KiB
C
1725 lines
43 KiB
C
/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2005 QLogic Corporation
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*
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* See LICENSE.qla2xxx for copyright and licensing details.
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*/
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#include "qla_def.h"
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#include <linux/delay.h>
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#include <asm/uaccess.h>
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static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
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static void qla2x00_nv_deselect(scsi_qla_host_t *);
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static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
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/*
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* NVRAM support routines
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*/
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/**
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* qla2x00_lock_nvram_access() -
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* @ha: HA context
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*/
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void
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qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
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{
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uint16_t data;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
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data = RD_REG_WORD(®->nvram);
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while (data & NVR_BUSY) {
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udelay(100);
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data = RD_REG_WORD(®->nvram);
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}
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/* Lock resource */
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WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
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RD_REG_WORD(®->u.isp2300.host_semaphore);
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udelay(5);
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data = RD_REG_WORD(®->u.isp2300.host_semaphore);
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while ((data & BIT_0) == 0) {
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/* Lock failed */
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udelay(100);
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WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
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RD_REG_WORD(®->u.isp2300.host_semaphore);
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udelay(5);
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data = RD_REG_WORD(®->u.isp2300.host_semaphore);
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}
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}
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}
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/**
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* qla2x00_unlock_nvram_access() -
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* @ha: HA context
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*/
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void
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qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
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WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
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RD_REG_WORD(®->u.isp2300.host_semaphore);
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}
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}
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/**
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* qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
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* request routine to get the word from NVRAM.
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* @ha: HA context
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* @addr: Address in NVRAM to read
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*
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* Returns the word read from nvram @addr.
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*/
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uint16_t
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qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
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{
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uint16_t data;
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uint32_t nv_cmd;
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nv_cmd = addr << 16;
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nv_cmd |= NV_READ_OP;
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data = qla2x00_nvram_request(ha, nv_cmd);
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return (data);
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}
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/**
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* qla2x00_write_nvram_word() - Write NVRAM data.
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* @ha: HA context
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* @addr: Address in NVRAM to write
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* @data: word to program
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*/
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void
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qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
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{
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int count;
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uint16_t word;
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uint32_t nv_cmd, wait_cnt;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Write data */
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nv_cmd = (addr << 16) | NV_WRITE_OP;
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nv_cmd |= data;
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nv_cmd <<= 5;
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for (count = 0; count < 27; count++) {
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if (nv_cmd & BIT_31)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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else
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qla2x00_nv_write(ha, 0);
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nv_cmd <<= 1;
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}
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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wait_cnt = NVR_WAIT_CNT;
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do {
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if (!--wait_cnt) {
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DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
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__func__, ha->host_no));
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break;
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}
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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qla2x00_nv_deselect(ha);
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/* Disable writes */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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for (count = 0; count < 10; count++)
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_deselect(ha);
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}
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static int
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qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
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uint32_t tmo)
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{
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int ret, count;
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uint16_t word;
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uint32_t nv_cmd;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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ret = QLA_SUCCESS;
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Write data */
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nv_cmd = (addr << 16) | NV_WRITE_OP;
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nv_cmd |= data;
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nv_cmd <<= 5;
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for (count = 0; count < 27; count++) {
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if (nv_cmd & BIT_31)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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else
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qla2x00_nv_write(ha, 0);
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nv_cmd <<= 1;
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}
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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if (!--tmo) {
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ret = QLA_FUNCTION_FAILED;
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break;
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}
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} while ((word & NVR_DATA_IN) == 0);
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qla2x00_nv_deselect(ha);
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/* Disable writes */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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for (count = 0; count < 10; count++)
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_deselect(ha);
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return ret;
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}
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/**
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* qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
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* NVRAM.
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* @ha: HA context
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* @nv_cmd: NVRAM command
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*
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* Bit definitions for NVRAM command:
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*
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* Bit 26 = start bit
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* Bit 25, 24 = opcode
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* Bit 23-16 = address
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* Bit 15-0 = write data
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*
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* Returns the word read from nvram @addr.
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*/
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static uint16_t
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qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
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{
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uint8_t cnt;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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uint16_t data = 0;
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uint16_t reg_data;
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/* Send command to NVRAM. */
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nv_cmd <<= 5;
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for (cnt = 0; cnt < 11; cnt++) {
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if (nv_cmd & BIT_31)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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else
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qla2x00_nv_write(ha, 0);
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nv_cmd <<= 1;
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}
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/* Read data from NVRAM. */
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for (cnt = 0; cnt < 16; cnt++) {
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WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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data <<= 1;
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reg_data = RD_REG_WORD(®->nvram);
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if (reg_data & NVR_DATA_IN)
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data |= BIT_0;
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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}
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/* Deselect chip. */
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WRT_REG_WORD(®->nvram, NVR_DESELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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return (data);
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}
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/**
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* qla2x00_nv_write() - Clean NVRAM operations.
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* @ha: HA context
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*/
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static void
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qla2x00_nv_deselect(scsi_qla_host_t *ha)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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WRT_REG_WORD(®->nvram, NVR_DESELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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}
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/**
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* qla2x00_nv_write() - Prepare for NVRAM read/write operation.
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* @ha: HA context
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* @data: Serial interface selector
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*/
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static void
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qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK |
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NVR_WRT_ENABLE);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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}
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/**
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* qla2x00_clear_nvram_protection() -
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* @ha: HA context
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*/
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static int
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qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
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{
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int ret, stat;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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uint32_t word, wait_cnt;
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uint16_t wprot, wprot_old;
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/* Clear NVRAM write protection. */
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ret = QLA_FUNCTION_FAILED;
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wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
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stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
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__constant_cpu_to_le16(0x1234), 100000);
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wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
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if (stat != QLA_SUCCESS || wprot != 0x1234) {
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/* Write enable. */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Enable protection register. */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Clear protection register (ffff is cleared). */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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wait_cnt = NVR_WAIT_CNT;
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do {
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if (!--wait_cnt) {
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DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
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"ready...\n", __func__,
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ha->host_no));
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break;
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}
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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if (wait_cnt)
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ret = QLA_SUCCESS;
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} else
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qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
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return ret;
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}
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static void
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qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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uint32_t word, wait_cnt;
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if (stat != QLA_SUCCESS)
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return;
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/* Set NVRAM write protection. */
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/* Write enable. */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Enable protection register. */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Enable protection register. */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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wait_cnt = NVR_WAIT_CNT;
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do {
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if (!--wait_cnt) {
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DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
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__func__, ha->host_no));
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break;
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}
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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}
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/*****************************************************************************/
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/* Flash Manipulation Routines */
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/*****************************************************************************/
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static inline uint32_t
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flash_conf_to_access_addr(uint32_t faddr)
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{
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return FARX_ACCESS_FLASH_CONF | faddr;
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}
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static inline uint32_t
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flash_data_to_access_addr(uint32_t faddr)
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{
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return FARX_ACCESS_FLASH_DATA | faddr;
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}
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static inline uint32_t
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nvram_conf_to_access_addr(uint32_t naddr)
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{
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return FARX_ACCESS_NVRAM_CONF | naddr;
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}
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static inline uint32_t
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nvram_data_to_access_addr(uint32_t naddr)
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{
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return FARX_ACCESS_NVRAM_DATA | naddr;
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}
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uint32_t
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qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
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{
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int rval;
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uint32_t cnt, data;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
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/* Wait for READ cycle to complete. */
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rval = QLA_SUCCESS;
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for (cnt = 3000;
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(RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
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rval == QLA_SUCCESS; cnt--) {
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if (cnt)
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udelay(10);
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else
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rval = QLA_FUNCTION_TIMEOUT;
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}
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/* TODO: What happens if we time out? */
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data = 0xDEADDEAD;
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if (rval == QLA_SUCCESS)
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data = RD_REG_DWORD(®->flash_data);
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return data;
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}
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uint32_t *
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qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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uint32_t dwords)
|
|
{
|
|
uint32_t i;
|
|
|
|
/* Dword reads to flash. */
|
|
for (i = 0; i < dwords; i++, faddr++)
|
|
dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
|
|
flash_data_to_access_addr(faddr)));
|
|
|
|
return dwptr;
|
|
}
|
|
|
|
int
|
|
qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
|
|
{
|
|
int rval;
|
|
uint32_t cnt;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
WRT_REG_DWORD(®->flash_data, data);
|
|
RD_REG_DWORD(®->flash_data); /* PCI Posting. */
|
|
WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
|
|
/* Wait for Write cycle to complete. */
|
|
rval = QLA_SUCCESS;
|
|
for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
|
|
rval == QLA_SUCCESS; cnt--) {
|
|
if (cnt)
|
|
udelay(10);
|
|
else
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
}
|
|
return rval;
|
|
}
|
|
|
|
void
|
|
qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
|
|
uint8_t *flash_id)
|
|
{
|
|
uint32_t ids;
|
|
|
|
ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
|
|
*man_id = LSB(ids);
|
|
*flash_id = MSB(ids);
|
|
|
|
/* Check if man_id and flash_id are valid. */
|
|
if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
|
|
/* Read information using 0x9f opcode
|
|
* Device ID, Mfg ID would be read in the format:
|
|
* <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
|
|
* Example: ATMEL 0x00 01 45 1F
|
|
* Extract MFG and Dev ID from last two bytes.
|
|
*/
|
|
ids = qla24xx_read_flash_dword(ha,
|
|
flash_data_to_access_addr(0xd009f));
|
|
*man_id = LSB(ids);
|
|
*flash_id = MSB(ids);
|
|
}
|
|
}
|
|
|
|
int
|
|
qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
|
|
uint32_t dwords)
|
|
{
|
|
int ret;
|
|
uint32_t liter;
|
|
uint32_t sec_mask, rest_addr, conf_addr, sec_end_mask;
|
|
uint32_t fdata, findex ;
|
|
uint8_t man_id, flash_id;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
ret = QLA_SUCCESS;
|
|
|
|
qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
|
|
DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
|
|
ha->host_no, man_id, flash_id));
|
|
|
|
sec_end_mask = 0;
|
|
conf_addr = flash_conf_to_access_addr(0x03d8);
|
|
switch (man_id) {
|
|
case 0xbf: /* STT flash. */
|
|
rest_addr = 0x1fff;
|
|
sec_mask = 0x3e000;
|
|
if (flash_id == 0x80)
|
|
conf_addr = flash_conf_to_access_addr(0x0352);
|
|
break;
|
|
case 0x13: /* ST M25P80. */
|
|
rest_addr = 0x3fff;
|
|
sec_mask = 0x3c000;
|
|
break;
|
|
case 0x1f: // Atmel 26DF081A
|
|
rest_addr = 0x0fff;
|
|
sec_mask = 0xff000;
|
|
sec_end_mask = 0x003ff;
|
|
conf_addr = flash_conf_to_access_addr(0x0320);
|
|
break;
|
|
default:
|
|
/* Default to 64 kb sector size. */
|
|
rest_addr = 0x3fff;
|
|
sec_mask = 0x3c000;
|
|
break;
|
|
}
|
|
|
|
/* Enable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
/* Disable flash write-protection. */
|
|
qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
|
|
/* Some flash parts need an additional zero-write to clear bits.*/
|
|
qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
|
|
|
|
do { /* Loop once to provide quick error exit. */
|
|
for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
|
|
if (man_id == 0x1f) {
|
|
findex = faddr << 2;
|
|
fdata = findex & sec_mask;
|
|
} else {
|
|
findex = faddr;
|
|
fdata = (findex & sec_mask) << 2;
|
|
}
|
|
|
|
/* Are we at the beginning of a sector? */
|
|
if ((findex & rest_addr) == 0) {
|
|
/*
|
|
* Do sector unprotect at 4K boundry for Atmel
|
|
* part.
|
|
*/
|
|
if (man_id == 0x1f)
|
|
qla24xx_write_flash_dword(ha,
|
|
flash_conf_to_access_addr(0x0339),
|
|
(fdata & 0xff00) | ((fdata << 16) &
|
|
0xff0000) | ((fdata >> 16) & 0xff));
|
|
fdata = (faddr & sec_mask) << 2;
|
|
ret = qla24xx_write_flash_dword(ha, conf_addr,
|
|
(fdata & 0xff00) |((fdata << 16) &
|
|
0xff0000) | ((fdata >> 16) & 0xff));
|
|
if (ret != QLA_SUCCESS) {
|
|
DEBUG9(printk("%s(%ld) Unable to flash "
|
|
"sector: address=%x.\n", __func__,
|
|
ha->host_no, faddr));
|
|
break;
|
|
}
|
|
}
|
|
ret = qla24xx_write_flash_dword(ha,
|
|
flash_data_to_access_addr(faddr),
|
|
cpu_to_le32(*dwptr));
|
|
if (ret != QLA_SUCCESS) {
|
|
DEBUG9(printk("%s(%ld) Unable to program flash "
|
|
"address=%x data=%x.\n", __func__,
|
|
ha->host_no, faddr, *dwptr));
|
|
break;
|
|
}
|
|
|
|
/* Do sector protect at 4K boundry for Atmel part. */
|
|
if (man_id == 0x1f &&
|
|
((faddr & sec_end_mask) == 0x3ff))
|
|
qla24xx_write_flash_dword(ha,
|
|
flash_conf_to_access_addr(0x0336),
|
|
(fdata & 0xff00) | ((fdata << 16) &
|
|
0xff0000) | ((fdata >> 16) & 0xff));
|
|
}
|
|
} while (0);
|
|
|
|
/* Enable flash write-protection. */
|
|
qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
|
|
|
|
/* Disable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
return ret;
|
|
}
|
|
|
|
uint8_t *
|
|
qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
uint32_t i;
|
|
uint16_t *wptr;
|
|
|
|
/* Word reads to NVRAM via registers. */
|
|
wptr = (uint16_t *)buf;
|
|
qla2x00_lock_nvram_access(ha);
|
|
for (i = 0; i < bytes >> 1; i++, naddr++)
|
|
wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
|
|
naddr));
|
|
qla2x00_unlock_nvram_access(ha);
|
|
|
|
return buf;
|
|
}
|
|
|
|
uint8_t *
|
|
qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
uint32_t i;
|
|
uint32_t *dwptr;
|
|
|
|
/* Dword reads to flash. */
|
|
dwptr = (uint32_t *)buf;
|
|
for (i = 0; i < bytes >> 2; i++, naddr++)
|
|
dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
|
|
nvram_data_to_access_addr(naddr)));
|
|
|
|
return buf;
|
|
}
|
|
|
|
int
|
|
qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
int ret, stat;
|
|
uint32_t i;
|
|
uint16_t *wptr;
|
|
|
|
ret = QLA_SUCCESS;
|
|
|
|
qla2x00_lock_nvram_access(ha);
|
|
|
|
/* Disable NVRAM write-protection. */
|
|
stat = qla2x00_clear_nvram_protection(ha);
|
|
|
|
wptr = (uint16_t *)buf;
|
|
for (i = 0; i < bytes >> 1; i++, naddr++) {
|
|
qla2x00_write_nvram_word(ha, naddr,
|
|
cpu_to_le16(*wptr));
|
|
wptr++;
|
|
}
|
|
|
|
/* Enable NVRAM write-protection. */
|
|
qla2x00_set_nvram_protection(ha, stat);
|
|
|
|
qla2x00_unlock_nvram_access(ha);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int
|
|
qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
int ret;
|
|
uint32_t i;
|
|
uint32_t *dwptr;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
ret = QLA_SUCCESS;
|
|
|
|
/* Enable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
/* Disable NVRAM write-protection. */
|
|
qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
|
|
0);
|
|
qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
|
|
0);
|
|
|
|
/* Dword writes to flash. */
|
|
dwptr = (uint32_t *)buf;
|
|
for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
|
|
ret = qla24xx_write_flash_dword(ha,
|
|
nvram_data_to_access_addr(naddr),
|
|
cpu_to_le32(*dwptr));
|
|
if (ret != QLA_SUCCESS) {
|
|
DEBUG9(printk("%s(%ld) Unable to program "
|
|
"nvram address=%x data=%x.\n", __func__,
|
|
ha->host_no, naddr, *dwptr));
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Enable NVRAM write-protection. */
|
|
qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
|
|
0x8c);
|
|
|
|
/* Disable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
static inline void
|
|
qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
|
|
{
|
|
if (IS_QLA2322(ha)) {
|
|
/* Flip all colors. */
|
|
if (ha->beacon_color_state == QLA_LED_ALL_ON) {
|
|
/* Turn off. */
|
|
ha->beacon_color_state = 0;
|
|
*pflags = GPIO_LED_ALL_OFF;
|
|
} else {
|
|
/* Turn on. */
|
|
ha->beacon_color_state = QLA_LED_ALL_ON;
|
|
*pflags = GPIO_LED_RGA_ON;
|
|
}
|
|
} else {
|
|
/* Flip green led only. */
|
|
if (ha->beacon_color_state == QLA_LED_GRN_ON) {
|
|
/* Turn off. */
|
|
ha->beacon_color_state = 0;
|
|
*pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
|
|
} else {
|
|
/* Turn on. */
|
|
ha->beacon_color_state = QLA_LED_GRN_ON;
|
|
*pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
qla2x00_beacon_blink(struct scsi_qla_host *ha)
|
|
{
|
|
uint16_t gpio_enable;
|
|
uint16_t gpio_data;
|
|
uint16_t led_color = 0;
|
|
unsigned long flags;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
|
|
if (ha->pio_address)
|
|
reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
|
|
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
|
|
/* Save the Original GPIOE. */
|
|
if (ha->pio_address) {
|
|
gpio_enable = RD_REG_WORD_PIO(®->gpioe);
|
|
gpio_data = RD_REG_WORD_PIO(®->gpiod);
|
|
} else {
|
|
gpio_enable = RD_REG_WORD(®->gpioe);
|
|
gpio_data = RD_REG_WORD(®->gpiod);
|
|
}
|
|
|
|
/* Set the modified gpio_enable values */
|
|
gpio_enable |= GPIO_LED_MASK;
|
|
|
|
if (ha->pio_address) {
|
|
WRT_REG_WORD_PIO(®->gpioe, gpio_enable);
|
|
} else {
|
|
WRT_REG_WORD(®->gpioe, gpio_enable);
|
|
RD_REG_WORD(®->gpioe);
|
|
}
|
|
|
|
qla2x00_flip_colors(ha, &led_color);
|
|
|
|
/* Clear out any previously set LED color. */
|
|
gpio_data &= ~GPIO_LED_MASK;
|
|
|
|
/* Set the new input LED color to GPIOD. */
|
|
gpio_data |= led_color;
|
|
|
|
/* Set the modified gpio_data values */
|
|
if (ha->pio_address) {
|
|
WRT_REG_WORD_PIO(®->gpiod, gpio_data);
|
|
} else {
|
|
WRT_REG_WORD(®->gpiod, gpio_data);
|
|
RD_REG_WORD(®->gpiod);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
int
|
|
qla2x00_beacon_on(struct scsi_qla_host *ha)
|
|
{
|
|
uint16_t gpio_enable;
|
|
uint16_t gpio_data;
|
|
unsigned long flags;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
|
|
ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
|
|
ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
|
|
|
|
if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
|
|
qla_printk(KERN_WARNING, ha,
|
|
"Unable to update fw options (beacon on).\n");
|
|
return QLA_FUNCTION_FAILED;
|
|
}
|
|
|
|
if (ha->pio_address)
|
|
reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
|
|
|
|
/* Turn off LEDs. */
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
if (ha->pio_address) {
|
|
gpio_enable = RD_REG_WORD_PIO(®->gpioe);
|
|
gpio_data = RD_REG_WORD_PIO(®->gpiod);
|
|
} else {
|
|
gpio_enable = RD_REG_WORD(®->gpioe);
|
|
gpio_data = RD_REG_WORD(®->gpiod);
|
|
}
|
|
gpio_enable |= GPIO_LED_MASK;
|
|
|
|
/* Set the modified gpio_enable values. */
|
|
if (ha->pio_address) {
|
|
WRT_REG_WORD_PIO(®->gpioe, gpio_enable);
|
|
} else {
|
|
WRT_REG_WORD(®->gpioe, gpio_enable);
|
|
RD_REG_WORD(®->gpioe);
|
|
}
|
|
|
|
/* Clear out previously set LED colour. */
|
|
gpio_data &= ~GPIO_LED_MASK;
|
|
if (ha->pio_address) {
|
|
WRT_REG_WORD_PIO(®->gpiod, gpio_data);
|
|
} else {
|
|
WRT_REG_WORD(®->gpiod, gpio_data);
|
|
RD_REG_WORD(®->gpiod);
|
|
}
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
|
|
/*
|
|
* Let the per HBA timer kick off the blinking process based on
|
|
* the following flags. No need to do anything else now.
|
|
*/
|
|
ha->beacon_blink_led = 1;
|
|
ha->beacon_color_state = 0;
|
|
|
|
return QLA_SUCCESS;
|
|
}
|
|
|
|
int
|
|
qla2x00_beacon_off(struct scsi_qla_host *ha)
|
|
{
|
|
int rval = QLA_SUCCESS;
|
|
|
|
ha->beacon_blink_led = 0;
|
|
|
|
/* Set the on flag so when it gets flipped it will be off. */
|
|
if (IS_QLA2322(ha))
|
|
ha->beacon_color_state = QLA_LED_ALL_ON;
|
|
else
|
|
ha->beacon_color_state = QLA_LED_GRN_ON;
|
|
|
|
ha->isp_ops.beacon_blink(ha); /* This turns green LED off */
|
|
|
|
ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
|
|
ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
|
|
|
|
rval = qla2x00_set_fw_options(ha, ha->fw_options);
|
|
if (rval != QLA_SUCCESS)
|
|
qla_printk(KERN_WARNING, ha,
|
|
"Unable to update fw options (beacon off).\n");
|
|
return rval;
|
|
}
|
|
|
|
|
|
static inline void
|
|
qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
|
|
{
|
|
/* Flip all colors. */
|
|
if (ha->beacon_color_state == QLA_LED_ALL_ON) {
|
|
/* Turn off. */
|
|
ha->beacon_color_state = 0;
|
|
*pflags = 0;
|
|
} else {
|
|
/* Turn on. */
|
|
ha->beacon_color_state = QLA_LED_ALL_ON;
|
|
*pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
|
|
}
|
|
}
|
|
|
|
void
|
|
qla24xx_beacon_blink(struct scsi_qla_host *ha)
|
|
{
|
|
uint16_t led_color = 0;
|
|
uint32_t gpio_data;
|
|
unsigned long flags;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
/* Save the Original GPIOD. */
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
gpio_data = RD_REG_DWORD(®->gpiod);
|
|
|
|
/* Enable the gpio_data reg for update. */
|
|
gpio_data |= GPDX_LED_UPDATE_MASK;
|
|
|
|
WRT_REG_DWORD(®->gpiod, gpio_data);
|
|
gpio_data = RD_REG_DWORD(®->gpiod);
|
|
|
|
/* Set the color bits. */
|
|
qla24xx_flip_colors(ha, &led_color);
|
|
|
|
/* Clear out any previously set LED color. */
|
|
gpio_data &= ~GPDX_LED_COLOR_MASK;
|
|
|
|
/* Set the new input LED color to GPIOD. */
|
|
gpio_data |= led_color;
|
|
|
|
/* Set the modified gpio_data values. */
|
|
WRT_REG_DWORD(®->gpiod, gpio_data);
|
|
gpio_data = RD_REG_DWORD(®->gpiod);
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
int
|
|
qla24xx_beacon_on(struct scsi_qla_host *ha)
|
|
{
|
|
uint32_t gpio_data;
|
|
unsigned long flags;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
if (ha->beacon_blink_led == 0) {
|
|
/* Enable firmware for update */
|
|
ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
|
|
|
|
if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
|
|
return QLA_FUNCTION_FAILED;
|
|
|
|
if (qla2x00_get_fw_options(ha, ha->fw_options) !=
|
|
QLA_SUCCESS) {
|
|
qla_printk(KERN_WARNING, ha,
|
|
"Unable to update fw options (beacon on).\n");
|
|
return QLA_FUNCTION_FAILED;
|
|
}
|
|
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
gpio_data = RD_REG_DWORD(®->gpiod);
|
|
|
|
/* Enable the gpio_data reg for update. */
|
|
gpio_data |= GPDX_LED_UPDATE_MASK;
|
|
WRT_REG_DWORD(®->gpiod, gpio_data);
|
|
RD_REG_DWORD(®->gpiod);
|
|
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
/* So all colors blink together. */
|
|
ha->beacon_color_state = 0;
|
|
|
|
/* Let the per HBA timer kick off the blinking process. */
|
|
ha->beacon_blink_led = 1;
|
|
|
|
return QLA_SUCCESS;
|
|
}
|
|
|
|
int
|
|
qla24xx_beacon_off(struct scsi_qla_host *ha)
|
|
{
|
|
uint32_t gpio_data;
|
|
unsigned long flags;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
ha->beacon_blink_led = 0;
|
|
ha->beacon_color_state = QLA_LED_ALL_ON;
|
|
|
|
ha->isp_ops.beacon_blink(ha); /* Will flip to all off. */
|
|
|
|
/* Give control back to firmware. */
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
gpio_data = RD_REG_DWORD(®->gpiod);
|
|
|
|
/* Disable the gpio_data reg for update. */
|
|
gpio_data &= ~GPDX_LED_UPDATE_MASK;
|
|
WRT_REG_DWORD(®->gpiod, gpio_data);
|
|
RD_REG_DWORD(®->gpiod);
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
|
|
ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
|
|
|
|
if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
|
|
qla_printk(KERN_WARNING, ha,
|
|
"Unable to update fw options (beacon off).\n");
|
|
return QLA_FUNCTION_FAILED;
|
|
}
|
|
|
|
if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
|
|
qla_printk(KERN_WARNING, ha,
|
|
"Unable to get fw options (beacon off).\n");
|
|
return QLA_FUNCTION_FAILED;
|
|
}
|
|
|
|
return QLA_SUCCESS;
|
|
}
|
|
|
|
|
|
/*
|
|
* Flash support routines
|
|
*/
|
|
|
|
/**
|
|
* qla2x00_flash_enable() - Setup flash for reading and writing.
|
|
* @ha: HA context
|
|
*/
|
|
static void
|
|
qla2x00_flash_enable(scsi_qla_host_t *ha)
|
|
{
|
|
uint16_t data;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
|
|
data = RD_REG_WORD(®->ctrl_status);
|
|
data |= CSR_FLASH_ENABLE;
|
|
WRT_REG_WORD(®->ctrl_status, data);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
}
|
|
|
|
/**
|
|
* qla2x00_flash_disable() - Disable flash and allow RISC to run.
|
|
* @ha: HA context
|
|
*/
|
|
static void
|
|
qla2x00_flash_disable(scsi_qla_host_t *ha)
|
|
{
|
|
uint16_t data;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
|
|
data = RD_REG_WORD(®->ctrl_status);
|
|
data &= ~(CSR_FLASH_ENABLE);
|
|
WRT_REG_WORD(®->ctrl_status, data);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
}
|
|
|
|
/**
|
|
* qla2x00_read_flash_byte() - Reads a byte from flash
|
|
* @ha: HA context
|
|
* @addr: Address in flash to read
|
|
*
|
|
* A word is read from the chip, but, only the lower byte is valid.
|
|
*
|
|
* Returns the byte read from flash @addr.
|
|
*/
|
|
static uint8_t
|
|
qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
|
|
{
|
|
uint16_t data;
|
|
uint16_t bank_select;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
|
|
bank_select = RD_REG_WORD(®->ctrl_status);
|
|
|
|
if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
|
|
/* Specify 64K address range: */
|
|
/* clear out Module Select and Flash Address bits [19:16]. */
|
|
bank_select &= ~0xf8;
|
|
bank_select |= addr >> 12 & 0xf0;
|
|
bank_select |= CSR_FLASH_64K_BANK;
|
|
WRT_REG_WORD(®->ctrl_status, bank_select);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
WRT_REG_WORD(®->flash_address, (uint16_t)addr);
|
|
data = RD_REG_WORD(®->flash_data);
|
|
|
|
return (uint8_t)data;
|
|
}
|
|
|
|
/* Setup bit 16 of flash address. */
|
|
if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
|
|
bank_select |= CSR_FLASH_64K_BANK;
|
|
WRT_REG_WORD(®->ctrl_status, bank_select);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
} else if (((addr & BIT_16) == 0) &&
|
|
(bank_select & CSR_FLASH_64K_BANK)) {
|
|
bank_select &= ~(CSR_FLASH_64K_BANK);
|
|
WRT_REG_WORD(®->ctrl_status, bank_select);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
}
|
|
|
|
/* Always perform IO mapped accesses to the FLASH registers. */
|
|
if (ha->pio_address) {
|
|
uint16_t data2;
|
|
|
|
reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
|
|
WRT_REG_WORD_PIO(®->flash_address, (uint16_t)addr);
|
|
do {
|
|
data = RD_REG_WORD_PIO(®->flash_data);
|
|
barrier();
|
|
cpu_relax();
|
|
data2 = RD_REG_WORD_PIO(®->flash_data);
|
|
} while (data != data2);
|
|
} else {
|
|
WRT_REG_WORD(®->flash_address, (uint16_t)addr);
|
|
data = qla2x00_debounce_register(®->flash_data);
|
|
}
|
|
|
|
return (uint8_t)data;
|
|
}
|
|
|
|
/**
|
|
* qla2x00_write_flash_byte() - Write a byte to flash
|
|
* @ha: HA context
|
|
* @addr: Address in flash to write
|
|
* @data: Data to write
|
|
*/
|
|
static void
|
|
qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
|
|
{
|
|
uint16_t bank_select;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
|
|
bank_select = RD_REG_WORD(®->ctrl_status);
|
|
if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
|
|
/* Specify 64K address range: */
|
|
/* clear out Module Select and Flash Address bits [19:16]. */
|
|
bank_select &= ~0xf8;
|
|
bank_select |= addr >> 12 & 0xf0;
|
|
bank_select |= CSR_FLASH_64K_BANK;
|
|
WRT_REG_WORD(®->ctrl_status, bank_select);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
WRT_REG_WORD(®->flash_address, (uint16_t)addr);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
WRT_REG_WORD(®->flash_data, (uint16_t)data);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
return;
|
|
}
|
|
|
|
/* Setup bit 16 of flash address. */
|
|
if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
|
|
bank_select |= CSR_FLASH_64K_BANK;
|
|
WRT_REG_WORD(®->ctrl_status, bank_select);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
} else if (((addr & BIT_16) == 0) &&
|
|
(bank_select & CSR_FLASH_64K_BANK)) {
|
|
bank_select &= ~(CSR_FLASH_64K_BANK);
|
|
WRT_REG_WORD(®->ctrl_status, bank_select);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
}
|
|
|
|
/* Always perform IO mapped accesses to the FLASH registers. */
|
|
if (ha->pio_address) {
|
|
reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
|
|
WRT_REG_WORD_PIO(®->flash_address, (uint16_t)addr);
|
|
WRT_REG_WORD_PIO(®->flash_data, (uint16_t)data);
|
|
} else {
|
|
WRT_REG_WORD(®->flash_address, (uint16_t)addr);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
WRT_REG_WORD(®->flash_data, (uint16_t)data);
|
|
RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
|
|
}
|
|
}
|
|
|
|
/**
|
|
* qla2x00_poll_flash() - Polls flash for completion.
|
|
* @ha: HA context
|
|
* @addr: Address in flash to poll
|
|
* @poll_data: Data to be polled
|
|
* @man_id: Flash manufacturer ID
|
|
* @flash_id: Flash ID
|
|
*
|
|
* This function polls the device until bit 7 of what is read matches data
|
|
* bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
|
|
* out (a fatal error). The flash book recommeds reading bit 7 again after
|
|
* reading bit 5 as a 1.
|
|
*
|
|
* Returns 0 on success, else non-zero.
|
|
*/
|
|
static int
|
|
qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
|
|
uint8_t man_id, uint8_t flash_id)
|
|
{
|
|
int status;
|
|
uint8_t flash_data;
|
|
uint32_t cnt;
|
|
|
|
status = 1;
|
|
|
|
/* Wait for 30 seconds for command to finish. */
|
|
poll_data &= BIT_7;
|
|
for (cnt = 3000000; cnt; cnt--) {
|
|
flash_data = qla2x00_read_flash_byte(ha, addr);
|
|
if ((flash_data & BIT_7) == poll_data) {
|
|
status = 0;
|
|
break;
|
|
}
|
|
|
|
if (man_id != 0x40 && man_id != 0xda) {
|
|
if ((flash_data & BIT_5) && cnt > 2)
|
|
cnt = 2;
|
|
}
|
|
udelay(10);
|
|
barrier();
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* qla2x00_program_flash_address() - Programs a flash address
|
|
* @ha: HA context
|
|
* @addr: Address in flash to program
|
|
* @data: Data to be written in flash
|
|
* @man_id: Flash manufacturer ID
|
|
* @flash_id: Flash ID
|
|
*
|
|
* Returns 0 on success, else non-zero.
|
|
*/
|
|
static int
|
|
qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
|
|
uint8_t man_id, uint8_t flash_id)
|
|
{
|
|
/* Write Program Command Sequence. */
|
|
if (IS_OEM_001(ha)) {
|
|
qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x555, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
|
|
qla2x00_write_flash_byte(ha, addr, data);
|
|
} else {
|
|
if (man_id == 0xda && flash_id == 0xc1) {
|
|
qla2x00_write_flash_byte(ha, addr, data);
|
|
if (addr & 0x7e)
|
|
return 0;
|
|
} else {
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
|
|
qla2x00_write_flash_byte(ha, addr, data);
|
|
}
|
|
}
|
|
|
|
udelay(150);
|
|
|
|
/* Wait for write to complete. */
|
|
return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
|
|
}
|
|
|
|
/**
|
|
* qla2x00_erase_flash() - Erase the flash.
|
|
* @ha: HA context
|
|
* @man_id: Flash manufacturer ID
|
|
* @flash_id: Flash ID
|
|
*
|
|
* Returns 0 on success, else non-zero.
|
|
*/
|
|
static int
|
|
qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
|
|
{
|
|
/* Individual Sector Erase Command Sequence */
|
|
if (IS_OEM_001(ha)) {
|
|
qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x555, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
|
|
qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x555, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
|
|
} else {
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0x80);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0x10);
|
|
}
|
|
|
|
udelay(150);
|
|
|
|
/* Wait for erase to complete. */
|
|
return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
|
|
}
|
|
|
|
/**
|
|
* qla2x00_erase_flash_sector() - Erase a flash sector.
|
|
* @ha: HA context
|
|
* @addr: Flash sector to erase
|
|
* @sec_mask: Sector address mask
|
|
* @man_id: Flash manufacturer ID
|
|
* @flash_id: Flash ID
|
|
*
|
|
* Returns 0 on success, else non-zero.
|
|
*/
|
|
static int
|
|
qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
|
|
uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
|
|
{
|
|
/* Individual Sector Erase Command Sequence */
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0x80);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
|
|
if (man_id == 0x1f && flash_id == 0x13)
|
|
qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
|
|
else
|
|
qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
|
|
|
|
udelay(150);
|
|
|
|
/* Wait for erase to complete. */
|
|
return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
|
|
}
|
|
|
|
/**
|
|
* qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
|
|
* @man_id: Flash manufacturer ID
|
|
* @flash_id: Flash ID
|
|
*/
|
|
static void
|
|
qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
|
|
uint8_t *flash_id)
|
|
{
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0x90);
|
|
*man_id = qla2x00_read_flash_byte(ha, 0x0000);
|
|
*flash_id = qla2x00_read_flash_byte(ha, 0x0001);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
|
|
qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
|
|
qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
|
|
}
|
|
|
|
|
|
static inline void
|
|
qla2x00_suspend_hba(struct scsi_qla_host *ha)
|
|
{
|
|
int cnt;
|
|
unsigned long flags;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
|
|
/* Suspend HBA. */
|
|
scsi_block_requests(ha->host);
|
|
ha->isp_ops.disable_intrs(ha);
|
|
set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
|
|
|
|
/* Pause RISC. */
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
|
|
RD_REG_WORD(®->hccr);
|
|
if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
|
|
for (cnt = 0; cnt < 30000; cnt++) {
|
|
if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
|
|
break;
|
|
udelay(100);
|
|
}
|
|
} else {
|
|
udelay(10);
|
|
}
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
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static inline void
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qla2x00_resume_hba(struct scsi_qla_host *ha)
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{
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/* Resume HBA. */
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clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
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qla2xxx_wake_dpc(ha);
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qla2x00_wait_for_hba_online(ha);
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scsi_unblock_requests(ha->host);
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}
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uint8_t *
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qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
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uint32_t offset, uint32_t length)
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{
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unsigned long flags;
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uint32_t addr, midpoint;
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uint8_t *data;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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/* Suspend HBA. */
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qla2x00_suspend_hba(ha);
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/* Go with read. */
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spin_lock_irqsave(&ha->hardware_lock, flags);
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midpoint = ha->optrom_size / 2;
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qla2x00_flash_enable(ha);
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WRT_REG_WORD(®->nvram, 0);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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for (addr = offset, data = buf; addr < length; addr++, data++) {
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if (addr == midpoint) {
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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}
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*data = qla2x00_read_flash_byte(ha, addr);
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}
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qla2x00_flash_disable(ha);
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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/* Resume HBA. */
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qla2x00_resume_hba(ha);
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return buf;
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}
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int
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qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
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uint32_t offset, uint32_t length)
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{
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int rval;
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unsigned long flags;
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uint8_t man_id, flash_id, sec_number, data;
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uint16_t wd;
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uint32_t addr, liter, sec_mask, rest_addr;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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/* Suspend HBA. */
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qla2x00_suspend_hba(ha);
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rval = QLA_SUCCESS;
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sec_number = 0;
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/* Reset ISP chip. */
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spin_lock_irqsave(&ha->hardware_lock, flags);
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WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
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pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
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/* Go with write. */
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qla2x00_flash_enable(ha);
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do { /* Loop once to provide quick error exit */
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/* Structure of flash memory based on manufacturer */
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if (IS_OEM_001(ha)) {
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/* OEM variant with special flash part. */
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man_id = flash_id = 0;
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rest_addr = 0xffff;
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sec_mask = 0x10000;
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goto update_flash;
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}
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qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
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switch (man_id) {
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case 0x20: /* ST flash. */
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if (flash_id == 0xd2 || flash_id == 0xe3) {
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/*
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* ST m29w008at part - 64kb sector size with
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* 32kb,8kb,8kb,16kb sectors at memory address
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* 0xf0000.
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*/
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rest_addr = 0xffff;
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sec_mask = 0x10000;
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break;
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}
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/*
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* ST m29w010b part - 16kb sector size
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* Default to 16kb sectors
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*/
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rest_addr = 0x3fff;
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sec_mask = 0x1c000;
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break;
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case 0x40: /* Mostel flash. */
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/* Mostel v29c51001 part - 512 byte sector size. */
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rest_addr = 0x1ff;
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sec_mask = 0x1fe00;
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break;
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case 0xbf: /* SST flash. */
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/* SST39sf10 part - 4kb sector size. */
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rest_addr = 0xfff;
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sec_mask = 0x1f000;
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break;
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case 0xda: /* Winbond flash. */
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/* Winbond W29EE011 part - 256 byte sector size. */
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rest_addr = 0x7f;
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sec_mask = 0x1ff80;
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break;
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case 0xc2: /* Macronix flash. */
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/* 64k sector size. */
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if (flash_id == 0x38 || flash_id == 0x4f) {
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rest_addr = 0xffff;
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sec_mask = 0x10000;
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break;
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}
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/* Fall through... */
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case 0x1f: /* Atmel flash. */
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/* 512k sector size. */
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if (flash_id == 0x13) {
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rest_addr = 0x7fffffff;
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sec_mask = 0x80000000;
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break;
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}
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/* Fall through... */
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case 0x01: /* AMD flash. */
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if (flash_id == 0x38 || flash_id == 0x40 ||
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flash_id == 0x4f) {
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/* Am29LV081 part - 64kb sector size. */
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/* Am29LV002BT part - 64kb sector size. */
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rest_addr = 0xffff;
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sec_mask = 0x10000;
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break;
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} else if (flash_id == 0x3e) {
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/*
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* Am29LV008b part - 64kb sector size with
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* 32kb,8kb,8kb,16kb sector at memory address
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* h0xf0000.
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*/
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rest_addr = 0xffff;
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sec_mask = 0x10000;
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break;
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} else if (flash_id == 0x20 || flash_id == 0x6e) {
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/*
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* Am29LV010 part or AM29f010 - 16kb sector
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* size.
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*/
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rest_addr = 0x3fff;
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sec_mask = 0x1c000;
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break;
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} else if (flash_id == 0x6d) {
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/* Am29LV001 part - 8kb sector size. */
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rest_addr = 0x1fff;
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sec_mask = 0x1e000;
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break;
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}
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default:
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/* Default to 16 kb sector size. */
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rest_addr = 0x3fff;
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sec_mask = 0x1c000;
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break;
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}
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update_flash:
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if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
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if (qla2x00_erase_flash(ha, man_id, flash_id)) {
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rval = QLA_FUNCTION_FAILED;
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break;
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}
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}
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for (addr = offset, liter = 0; liter < length; liter++,
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addr++) {
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data = buf[liter];
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/* Are we at the beginning of a sector? */
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if ((addr & rest_addr) == 0) {
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if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
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if (addr >= 0x10000UL) {
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if (((addr >> 12) & 0xf0) &&
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((man_id == 0x01 &&
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flash_id == 0x3e) ||
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(man_id == 0x20 &&
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flash_id == 0xd2))) {
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sec_number++;
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if (sec_number == 1) {
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rest_addr =
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0x7fff;
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sec_mask =
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0x18000;
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} else if (
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sec_number == 2 ||
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sec_number == 3) {
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rest_addr =
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0x1fff;
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sec_mask =
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0x1e000;
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} else if (
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sec_number == 4) {
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rest_addr =
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0x3fff;
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sec_mask =
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0x1c000;
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}
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}
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}
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} else if (addr == ha->optrom_size / 2) {
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram);
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}
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if (flash_id == 0xda && man_id == 0xc1) {
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qla2x00_write_flash_byte(ha, 0x5555,
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0xaa);
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qla2x00_write_flash_byte(ha, 0x2aaa,
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0x55);
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qla2x00_write_flash_byte(ha, 0x5555,
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0xa0);
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} else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
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/* Then erase it */
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if (qla2x00_erase_flash_sector(ha,
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addr, sec_mask, man_id,
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flash_id)) {
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rval = QLA_FUNCTION_FAILED;
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break;
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}
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if (man_id == 0x01 && flash_id == 0x6d)
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sec_number++;
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}
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}
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if (man_id == 0x01 && flash_id == 0x6d) {
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if (sec_number == 1 &&
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addr == (rest_addr - 1)) {
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rest_addr = 0x0fff;
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sec_mask = 0x1f000;
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} else if (sec_number == 3 && (addr & 0x7ffe)) {
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rest_addr = 0x3fff;
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sec_mask = 0x1c000;
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}
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}
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if (qla2x00_program_flash_address(ha, addr, data,
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man_id, flash_id)) {
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rval = QLA_FUNCTION_FAILED;
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break;
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}
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}
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} while (0);
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qla2x00_flash_disable(ha);
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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/* Resume HBA. */
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qla2x00_resume_hba(ha);
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return rval;
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}
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uint8_t *
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qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
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uint32_t offset, uint32_t length)
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{
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/* Suspend HBA. */
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scsi_block_requests(ha->host);
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ha->isp_ops.disable_intrs(ha);
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set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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/* Go with read. */
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qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
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/* Resume HBA. */
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clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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ha->isp_ops.enable_intrs(ha);
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scsi_unblock_requests(ha->host);
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return buf;
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}
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int
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qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
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uint32_t offset, uint32_t length)
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{
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int rval;
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/* Suspend HBA. */
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scsi_block_requests(ha->host);
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ha->isp_ops.disable_intrs(ha);
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set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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/* Go with write. */
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rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
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length >> 2);
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/* Resume HBA -- RISC reset needed. */
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clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
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qla2xxx_wake_dpc(ha);
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qla2x00_wait_for_hba_online(ha);
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scsi_unblock_requests(ha->host);
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return rval;
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}
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