1148 lines
27 KiB
C
1148 lines
27 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2009, 2010 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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/*
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* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
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* using the CPU's debug registers.
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*/
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#define pr_fmt(fmt) "hw-breakpoint: " fmt
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#include <linux/errno.h>
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#include <linux/hardirq.h>
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#include <linux/perf_event.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/smp.h>
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#include <linux/cpu_pm.h>
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#include <linux/coresight.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/current.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/traps.h>
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/* Breakpoint currently in use for each BRP. */
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static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
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/* Watchpoint currently in use for each WRP. */
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static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
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/* Number of BRP/WRP registers on this CPU. */
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static int core_num_brps __ro_after_init;
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static int core_num_wrps __ro_after_init;
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/* Debug architecture version. */
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static u8 debug_arch __ro_after_init;
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/* Does debug architecture support OS Save and Restore? */
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static bool has_ossr __ro_after_init;
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/* Maximum supported watchpoint length. */
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static u8 max_watchpoint_len __ro_after_init;
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#define READ_WB_REG_CASE(OP2, M, VAL) \
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case ((OP2 << 4) + M): \
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ARM_DBG_READ(c0, c ## M, OP2, VAL); \
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break
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#define WRITE_WB_REG_CASE(OP2, M, VAL) \
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case ((OP2 << 4) + M): \
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ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
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break
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#define GEN_READ_WB_REG_CASES(OP2, VAL) \
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READ_WB_REG_CASE(OP2, 0, VAL); \
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READ_WB_REG_CASE(OP2, 1, VAL); \
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READ_WB_REG_CASE(OP2, 2, VAL); \
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READ_WB_REG_CASE(OP2, 3, VAL); \
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READ_WB_REG_CASE(OP2, 4, VAL); \
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READ_WB_REG_CASE(OP2, 5, VAL); \
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READ_WB_REG_CASE(OP2, 6, VAL); \
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READ_WB_REG_CASE(OP2, 7, VAL); \
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READ_WB_REG_CASE(OP2, 8, VAL); \
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READ_WB_REG_CASE(OP2, 9, VAL); \
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READ_WB_REG_CASE(OP2, 10, VAL); \
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READ_WB_REG_CASE(OP2, 11, VAL); \
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READ_WB_REG_CASE(OP2, 12, VAL); \
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READ_WB_REG_CASE(OP2, 13, VAL); \
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READ_WB_REG_CASE(OP2, 14, VAL); \
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READ_WB_REG_CASE(OP2, 15, VAL)
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#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
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WRITE_WB_REG_CASE(OP2, 0, VAL); \
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WRITE_WB_REG_CASE(OP2, 1, VAL); \
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WRITE_WB_REG_CASE(OP2, 2, VAL); \
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WRITE_WB_REG_CASE(OP2, 3, VAL); \
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WRITE_WB_REG_CASE(OP2, 4, VAL); \
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WRITE_WB_REG_CASE(OP2, 5, VAL); \
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WRITE_WB_REG_CASE(OP2, 6, VAL); \
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WRITE_WB_REG_CASE(OP2, 7, VAL); \
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WRITE_WB_REG_CASE(OP2, 8, VAL); \
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WRITE_WB_REG_CASE(OP2, 9, VAL); \
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WRITE_WB_REG_CASE(OP2, 10, VAL); \
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WRITE_WB_REG_CASE(OP2, 11, VAL); \
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WRITE_WB_REG_CASE(OP2, 12, VAL); \
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WRITE_WB_REG_CASE(OP2, 13, VAL); \
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WRITE_WB_REG_CASE(OP2, 14, VAL); \
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WRITE_WB_REG_CASE(OP2, 15, VAL)
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static u32 read_wb_reg(int n)
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{
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u32 val = 0;
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switch (n) {
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GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
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GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
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GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
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GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
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default:
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pr_warn("attempt to read from unknown breakpoint register %d\n",
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n);
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}
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return val;
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}
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static void write_wb_reg(int n, u32 val)
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{
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switch (n) {
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GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
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GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
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GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
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GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
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default:
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pr_warn("attempt to write to unknown breakpoint register %d\n",
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n);
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}
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isb();
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}
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/* Determine debug architecture. */
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static u8 get_debug_arch(void)
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{
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u32 didr;
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/* Do we implement the extended CPUID interface? */
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if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
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pr_warn_once("CPUID feature registers not supported. "
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"Assuming v6 debug is present.\n");
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return ARM_DEBUG_ARCH_V6;
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}
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ARM_DBG_READ(c0, c0, 0, didr);
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return (didr >> 16) & 0xf;
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}
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u8 arch_get_debug_arch(void)
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{
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return debug_arch;
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}
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static int debug_arch_supported(void)
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{
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u8 arch = get_debug_arch();
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/* We don't support the memory-mapped interface. */
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return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
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arch >= ARM_DEBUG_ARCH_V7_1;
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}
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/* Can we determine the watchpoint access type from the fsr? */
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static int debug_exception_updates_fsr(void)
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{
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return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
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}
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/* Determine number of WRP registers available. */
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static int get_num_wrp_resources(void)
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{
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u32 didr;
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ARM_DBG_READ(c0, c0, 0, didr);
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return ((didr >> 28) & 0xf) + 1;
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}
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/* Determine number of BRP registers available. */
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static int get_num_brp_resources(void)
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{
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u32 didr;
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ARM_DBG_READ(c0, c0, 0, didr);
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return ((didr >> 24) & 0xf) + 1;
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}
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/* Does this core support mismatch breakpoints? */
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static int core_has_mismatch_brps(void)
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{
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return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
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get_num_brp_resources() > 1);
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}
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/* Determine number of usable WRPs available. */
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static int get_num_wrps(void)
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{
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/*
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* On debug architectures prior to 7.1, when a watchpoint fires, the
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* only way to work out which watchpoint it was is by disassembling
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* the faulting instruction and working out the address of the memory
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* access.
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*
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* Furthermore, we can only do this if the watchpoint was precise
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* since imprecise watchpoints prevent us from calculating register
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* based addresses.
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*
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* Providing we have more than 1 breakpoint register, we only report
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* a single watchpoint register for the time being. This way, we always
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* know which watchpoint fired. In the future we can either add a
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* disassembler and address generation emulator, or we can insert a
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* check to see if the DFAR is set on watchpoint exception entry
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* [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
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* that it is set on some implementations].
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*/
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if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
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return 1;
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return get_num_wrp_resources();
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}
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/* Determine number of usable BRPs available. */
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static int get_num_brps(void)
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{
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int brps = get_num_brp_resources();
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return core_has_mismatch_brps() ? brps - 1 : brps;
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}
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/*
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* In order to access the breakpoint/watchpoint control registers,
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* we must be running in debug monitor mode. Unfortunately, we can
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* be put into halting debug mode at any time by an external debugger
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* but there is nothing we can do to prevent that.
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*/
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static int monitor_mode_enabled(void)
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{
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u32 dscr;
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ARM_DBG_READ(c0, c1, 0, dscr);
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return !!(dscr & ARM_DSCR_MDBGEN);
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}
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static int enable_monitor_mode(void)
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{
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u32 dscr;
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ARM_DBG_READ(c0, c1, 0, dscr);
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/* If monitor mode is already enabled, just return. */
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if (dscr & ARM_DSCR_MDBGEN)
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goto out;
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/* Write to the corresponding DSCR. */
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switch (get_debug_arch()) {
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case ARM_DEBUG_ARCH_V6:
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case ARM_DEBUG_ARCH_V6_1:
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ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
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break;
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case ARM_DEBUG_ARCH_V7_ECP14:
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case ARM_DEBUG_ARCH_V7_1:
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case ARM_DEBUG_ARCH_V8:
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ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
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isb();
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break;
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default:
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return -ENODEV;
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}
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/* Check that the write made it through. */
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ARM_DBG_READ(c0, c1, 0, dscr);
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if (!(dscr & ARM_DSCR_MDBGEN)) {
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pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
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smp_processor_id());
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return -EPERM;
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}
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out:
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return 0;
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}
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int hw_breakpoint_slots(int type)
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{
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if (!debug_arch_supported())
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return 0;
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/*
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* We can be called early, so don't rely on
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* our static variables being initialised.
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*/
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switch (type) {
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case TYPE_INST:
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return get_num_brps();
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case TYPE_DATA:
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return get_num_wrps();
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default:
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pr_warn("unknown slot type: %d\n", type);
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return 0;
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}
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}
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/*
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* Check if 8-bit byte-address select is available.
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* This clobbers WRP 0.
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*/
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static u8 get_max_wp_len(void)
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{
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u32 ctrl_reg;
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struct arch_hw_breakpoint_ctrl ctrl;
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u8 size = 4;
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if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
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goto out;
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memset(&ctrl, 0, sizeof(ctrl));
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ctrl.len = ARM_BREAKPOINT_LEN_8;
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ctrl_reg = encode_ctrl_reg(ctrl);
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write_wb_reg(ARM_BASE_WVR, 0);
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write_wb_reg(ARM_BASE_WCR, ctrl_reg);
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if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
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size = 8;
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out:
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return size;
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}
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u8 arch_get_max_wp_len(void)
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{
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return max_watchpoint_len;
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}
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/*
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* Install a perf counter breakpoint.
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*/
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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struct perf_event **slot, **slots;
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int i, max_slots, ctrl_base, val_base;
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u32 addr, ctrl;
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addr = info->address;
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ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
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if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
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/* Breakpoint */
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ctrl_base = ARM_BASE_BCR;
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val_base = ARM_BASE_BVR;
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slots = this_cpu_ptr(bp_on_reg);
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max_slots = core_num_brps;
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} else {
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/* Watchpoint */
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ctrl_base = ARM_BASE_WCR;
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val_base = ARM_BASE_WVR;
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slots = this_cpu_ptr(wp_on_reg);
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max_slots = core_num_wrps;
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}
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for (i = 0; i < max_slots; ++i) {
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slot = &slots[i];
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if (!*slot) {
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*slot = bp;
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break;
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}
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}
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if (i == max_slots) {
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pr_warn("Can't find any breakpoint slot\n");
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return -EBUSY;
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}
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/* Override the breakpoint data with the step data. */
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if (info->step_ctrl.enabled) {
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addr = info->trigger & ~0x3;
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ctrl = encode_ctrl_reg(info->step_ctrl);
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if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
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i = 0;
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ctrl_base = ARM_BASE_BCR + core_num_brps;
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val_base = ARM_BASE_BVR + core_num_brps;
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}
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}
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/* Setup the address register. */
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write_wb_reg(val_base + i, addr);
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/* Setup the control register. */
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write_wb_reg(ctrl_base + i, ctrl);
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return 0;
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}
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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struct perf_event **slot, **slots;
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int i, max_slots, base;
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if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
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/* Breakpoint */
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base = ARM_BASE_BCR;
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slots = this_cpu_ptr(bp_on_reg);
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max_slots = core_num_brps;
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} else {
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/* Watchpoint */
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base = ARM_BASE_WCR;
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slots = this_cpu_ptr(wp_on_reg);
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max_slots = core_num_wrps;
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}
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/* Remove the breakpoint. */
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for (i = 0; i < max_slots; ++i) {
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slot = &slots[i];
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if (*slot == bp) {
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*slot = NULL;
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break;
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}
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}
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if (i == max_slots) {
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pr_warn("Can't find any breakpoint slot\n");
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return;
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}
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/* Ensure that we disable the mismatch breakpoint. */
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if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
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info->step_ctrl.enabled) {
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i = 0;
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base = ARM_BASE_BCR + core_num_brps;
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}
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/* Reset the control register. */
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write_wb_reg(base + i, 0);
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}
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static int get_hbp_len(u8 hbp_len)
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{
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unsigned int len_in_bytes = 0;
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switch (hbp_len) {
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case ARM_BREAKPOINT_LEN_1:
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len_in_bytes = 1;
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break;
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case ARM_BREAKPOINT_LEN_2:
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len_in_bytes = 2;
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break;
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case ARM_BREAKPOINT_LEN_4:
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len_in_bytes = 4;
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break;
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case ARM_BREAKPOINT_LEN_8:
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len_in_bytes = 8;
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break;
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}
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return len_in_bytes;
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}
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|
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/*
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* Check whether bp virtual address is in kernel space.
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*/
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int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
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{
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unsigned int len;
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unsigned long va;
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va = hw->address;
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len = get_hbp_len(hw->ctrl.len);
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return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
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}
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/*
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* Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
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* Hopefully this will disappear when ptrace can bypass the conversion
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* to generic breakpoint descriptions.
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*/
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int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
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int *gen_len, int *gen_type)
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{
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/* Type */
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switch (ctrl.type) {
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case ARM_BREAKPOINT_EXECUTE:
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*gen_type = HW_BREAKPOINT_X;
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break;
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case ARM_BREAKPOINT_LOAD:
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*gen_type = HW_BREAKPOINT_R;
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break;
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case ARM_BREAKPOINT_STORE:
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*gen_type = HW_BREAKPOINT_W;
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break;
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case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
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*gen_type = HW_BREAKPOINT_RW;
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break;
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default:
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return -EINVAL;
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}
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|
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/* Len */
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switch (ctrl.len) {
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case ARM_BREAKPOINT_LEN_1:
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*gen_len = HW_BREAKPOINT_LEN_1;
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break;
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case ARM_BREAKPOINT_LEN_2:
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*gen_len = HW_BREAKPOINT_LEN_2;
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break;
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case ARM_BREAKPOINT_LEN_4:
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*gen_len = HW_BREAKPOINT_LEN_4;
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break;
|
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case ARM_BREAKPOINT_LEN_8:
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*gen_len = HW_BREAKPOINT_LEN_8;
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break;
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default:
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return -EINVAL;
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}
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|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Construct an arch_hw_breakpoint from a perf_event.
|
|
*/
|
|
static int arch_build_bp_info(struct perf_event *bp,
|
|
const struct perf_event_attr *attr,
|
|
struct arch_hw_breakpoint *hw)
|
|
{
|
|
/* Type */
|
|
switch (attr->bp_type) {
|
|
case HW_BREAKPOINT_X:
|
|
hw->ctrl.type = ARM_BREAKPOINT_EXECUTE;
|
|
break;
|
|
case HW_BREAKPOINT_R:
|
|
hw->ctrl.type = ARM_BREAKPOINT_LOAD;
|
|
break;
|
|
case HW_BREAKPOINT_W:
|
|
hw->ctrl.type = ARM_BREAKPOINT_STORE;
|
|
break;
|
|
case HW_BREAKPOINT_RW:
|
|
hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Len */
|
|
switch (attr->bp_len) {
|
|
case HW_BREAKPOINT_LEN_1:
|
|
hw->ctrl.len = ARM_BREAKPOINT_LEN_1;
|
|
break;
|
|
case HW_BREAKPOINT_LEN_2:
|
|
hw->ctrl.len = ARM_BREAKPOINT_LEN_2;
|
|
break;
|
|
case HW_BREAKPOINT_LEN_4:
|
|
hw->ctrl.len = ARM_BREAKPOINT_LEN_4;
|
|
break;
|
|
case HW_BREAKPOINT_LEN_8:
|
|
hw->ctrl.len = ARM_BREAKPOINT_LEN_8;
|
|
if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
|
|
&& max_watchpoint_len >= 8)
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
|
|
* Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
|
|
* by the hardware and must be aligned to the appropriate number of
|
|
* bytes.
|
|
*/
|
|
if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
|
|
hw->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
|
|
hw->ctrl.len != ARM_BREAKPOINT_LEN_4)
|
|
return -EINVAL;
|
|
|
|
/* Address */
|
|
hw->address = attr->bp_addr;
|
|
|
|
/* Privilege */
|
|
hw->ctrl.privilege = ARM_BREAKPOINT_USER;
|
|
if (arch_check_bp_in_kernelspace(hw))
|
|
hw->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
|
|
|
|
/* Enabled? */
|
|
hw->ctrl.enabled = !attr->disabled;
|
|
|
|
/* Mismatch */
|
|
hw->ctrl.mismatch = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Validate the arch-specific HW Breakpoint register settings.
|
|
*/
|
|
int hw_breakpoint_arch_parse(struct perf_event *bp,
|
|
const struct perf_event_attr *attr,
|
|
struct arch_hw_breakpoint *hw)
|
|
{
|
|
int ret = 0;
|
|
u32 offset, alignment_mask = 0x3;
|
|
|
|
/* Ensure that we are in monitor debug mode. */
|
|
if (!monitor_mode_enabled())
|
|
return -ENODEV;
|
|
|
|
/* Build the arch_hw_breakpoint. */
|
|
ret = arch_build_bp_info(bp, attr, hw);
|
|
if (ret)
|
|
goto out;
|
|
|
|
/* Check address alignment. */
|
|
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_8)
|
|
alignment_mask = 0x7;
|
|
offset = hw->address & alignment_mask;
|
|
switch (offset) {
|
|
case 0:
|
|
/* Aligned */
|
|
break;
|
|
case 1:
|
|
case 2:
|
|
/* Allow halfword watchpoints and breakpoints. */
|
|
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
|
|
break;
|
|
case 3:
|
|
/* Allow single byte watchpoint. */
|
|
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
hw->address &= ~alignment_mask;
|
|
hw->ctrl.len <<= offset;
|
|
|
|
if (is_default_overflow_handler(bp)) {
|
|
/*
|
|
* Mismatch breakpoints are required for single-stepping
|
|
* breakpoints.
|
|
*/
|
|
if (!core_has_mismatch_brps())
|
|
return -EINVAL;
|
|
|
|
/* We don't allow mismatch breakpoints in kernel space. */
|
|
if (arch_check_bp_in_kernelspace(hw))
|
|
return -EPERM;
|
|
|
|
/*
|
|
* Per-cpu breakpoints are not supported by our stepping
|
|
* mechanism.
|
|
*/
|
|
if (!bp->hw.target)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* We only support specific access types if the fsr
|
|
* reports them.
|
|
*/
|
|
if (!debug_exception_updates_fsr() &&
|
|
(hw->ctrl.type == ARM_BREAKPOINT_LOAD ||
|
|
hw->ctrl.type == ARM_BREAKPOINT_STORE))
|
|
return -EINVAL;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Enable/disable single-stepping over the breakpoint bp at address addr.
|
|
*/
|
|
static void enable_single_step(struct perf_event *bp, u32 addr)
|
|
{
|
|
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
|
|
|
arch_uninstall_hw_breakpoint(bp);
|
|
info->step_ctrl.mismatch = 1;
|
|
info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
|
|
info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
|
|
info->step_ctrl.privilege = info->ctrl.privilege;
|
|
info->step_ctrl.enabled = 1;
|
|
info->trigger = addr;
|
|
arch_install_hw_breakpoint(bp);
|
|
}
|
|
|
|
static void disable_single_step(struct perf_event *bp)
|
|
{
|
|
arch_uninstall_hw_breakpoint(bp);
|
|
counter_arch_bp(bp)->step_ctrl.enabled = 0;
|
|
arch_install_hw_breakpoint(bp);
|
|
}
|
|
|
|
static void watchpoint_handler(unsigned long addr, unsigned int fsr,
|
|
struct pt_regs *regs)
|
|
{
|
|
int i, access;
|
|
u32 val, ctrl_reg, alignment_mask;
|
|
struct perf_event *wp, **slots;
|
|
struct arch_hw_breakpoint *info;
|
|
struct arch_hw_breakpoint_ctrl ctrl;
|
|
|
|
slots = this_cpu_ptr(wp_on_reg);
|
|
|
|
for (i = 0; i < core_num_wrps; ++i) {
|
|
rcu_read_lock();
|
|
|
|
wp = slots[i];
|
|
|
|
if (wp == NULL)
|
|
goto unlock;
|
|
|
|
info = counter_arch_bp(wp);
|
|
/*
|
|
* The DFAR is an unknown value on debug architectures prior
|
|
* to 7.1. Since we only allow a single watchpoint on these
|
|
* older CPUs, we can set the trigger to the lowest possible
|
|
* faulting address.
|
|
*/
|
|
if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
|
|
BUG_ON(i > 0);
|
|
info->trigger = wp->attr.bp_addr;
|
|
} else {
|
|
if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
|
|
alignment_mask = 0x7;
|
|
else
|
|
alignment_mask = 0x3;
|
|
|
|
/* Check if the watchpoint value matches. */
|
|
val = read_wb_reg(ARM_BASE_WVR + i);
|
|
if (val != (addr & ~alignment_mask))
|
|
goto unlock;
|
|
|
|
/* Possible match, check the byte address select. */
|
|
ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
|
|
decode_ctrl_reg(ctrl_reg, &ctrl);
|
|
if (!((1 << (addr & alignment_mask)) & ctrl.len))
|
|
goto unlock;
|
|
|
|
/* Check that the access type matches. */
|
|
if (debug_exception_updates_fsr()) {
|
|
access = (fsr & ARM_FSR_ACCESS_MASK) ?
|
|
HW_BREAKPOINT_W : HW_BREAKPOINT_R;
|
|
if (!(access & hw_breakpoint_type(wp)))
|
|
goto unlock;
|
|
}
|
|
|
|
/* We have a winner. */
|
|
info->trigger = addr;
|
|
}
|
|
|
|
pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
|
|
perf_bp_event(wp, regs);
|
|
|
|
/*
|
|
* If no overflow handler is present, insert a temporary
|
|
* mismatch breakpoint so we can single-step over the
|
|
* watchpoint trigger.
|
|
*/
|
|
if (is_default_overflow_handler(wp))
|
|
enable_single_step(wp, instruction_pointer(regs));
|
|
|
|
unlock:
|
|
rcu_read_unlock();
|
|
}
|
|
}
|
|
|
|
static void watchpoint_single_step_handler(unsigned long pc)
|
|
{
|
|
int i;
|
|
struct perf_event *wp, **slots;
|
|
struct arch_hw_breakpoint *info;
|
|
|
|
slots = this_cpu_ptr(wp_on_reg);
|
|
|
|
for (i = 0; i < core_num_wrps; ++i) {
|
|
rcu_read_lock();
|
|
|
|
wp = slots[i];
|
|
|
|
if (wp == NULL)
|
|
goto unlock;
|
|
|
|
info = counter_arch_bp(wp);
|
|
if (!info->step_ctrl.enabled)
|
|
goto unlock;
|
|
|
|
/*
|
|
* Restore the original watchpoint if we've completed the
|
|
* single-step.
|
|
*/
|
|
if (info->trigger != pc)
|
|
disable_single_step(wp);
|
|
|
|
unlock:
|
|
rcu_read_unlock();
|
|
}
|
|
}
|
|
|
|
static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
|
|
{
|
|
int i;
|
|
u32 ctrl_reg, val, addr;
|
|
struct perf_event *bp, **slots;
|
|
struct arch_hw_breakpoint *info;
|
|
struct arch_hw_breakpoint_ctrl ctrl;
|
|
|
|
slots = this_cpu_ptr(bp_on_reg);
|
|
|
|
/* The exception entry code places the amended lr in the PC. */
|
|
addr = regs->ARM_pc;
|
|
|
|
/* Check the currently installed breakpoints first. */
|
|
for (i = 0; i < core_num_brps; ++i) {
|
|
rcu_read_lock();
|
|
|
|
bp = slots[i];
|
|
|
|
if (bp == NULL)
|
|
goto unlock;
|
|
|
|
info = counter_arch_bp(bp);
|
|
|
|
/* Check if the breakpoint value matches. */
|
|
val = read_wb_reg(ARM_BASE_BVR + i);
|
|
if (val != (addr & ~0x3))
|
|
goto mismatch;
|
|
|
|
/* Possible match, check the byte address select to confirm. */
|
|
ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
|
|
decode_ctrl_reg(ctrl_reg, &ctrl);
|
|
if ((1 << (addr & 0x3)) & ctrl.len) {
|
|
info->trigger = addr;
|
|
pr_debug("breakpoint fired: address = 0x%x\n", addr);
|
|
perf_bp_event(bp, regs);
|
|
if (!bp->overflow_handler)
|
|
enable_single_step(bp, addr);
|
|
goto unlock;
|
|
}
|
|
|
|
mismatch:
|
|
/* If we're stepping a breakpoint, it can now be restored. */
|
|
if (info->step_ctrl.enabled)
|
|
disable_single_step(bp);
|
|
unlock:
|
|
rcu_read_unlock();
|
|
}
|
|
|
|
/* Handle any pending watchpoint single-step breakpoints. */
|
|
watchpoint_single_step_handler(addr);
|
|
}
|
|
|
|
/*
|
|
* Called from either the Data Abort Handler [watchpoint] or the
|
|
* Prefetch Abort Handler [breakpoint] with interrupts disabled.
|
|
*/
|
|
static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
|
|
struct pt_regs *regs)
|
|
{
|
|
int ret = 0;
|
|
u32 dscr;
|
|
|
|
preempt_disable();
|
|
|
|
if (interrupts_enabled(regs))
|
|
local_irq_enable();
|
|
|
|
/* We only handle watchpoints and hardware breakpoints. */
|
|
ARM_DBG_READ(c0, c1, 0, dscr);
|
|
|
|
/* Perform perf callbacks. */
|
|
switch (ARM_DSCR_MOE(dscr)) {
|
|
case ARM_ENTRY_BREAKPOINT:
|
|
breakpoint_handler(addr, regs);
|
|
break;
|
|
case ARM_ENTRY_ASYNC_WATCHPOINT:
|
|
WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
|
|
case ARM_ENTRY_SYNC_WATCHPOINT:
|
|
watchpoint_handler(addr, fsr, regs);
|
|
break;
|
|
default:
|
|
ret = 1; /* Unhandled fault. */
|
|
}
|
|
|
|
preempt_enable();
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* One-time initialisation.
|
|
*/
|
|
static cpumask_t debug_err_mask;
|
|
|
|
static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
|
|
instr, cpu);
|
|
|
|
/* Set the error flag for this CPU and skip the faulting instruction. */
|
|
cpumask_set_cpu(cpu, &debug_err_mask);
|
|
instruction_pointer(regs) += 4;
|
|
return 0;
|
|
}
|
|
|
|
static struct undef_hook debug_reg_hook = {
|
|
.instr_mask = 0x0fe80f10,
|
|
.instr_val = 0x0e000e10,
|
|
.fn = debug_reg_trap,
|
|
};
|
|
|
|
/* Does this core support OS Save and Restore? */
|
|
static bool core_has_os_save_restore(void)
|
|
{
|
|
u32 oslsr;
|
|
|
|
switch (get_debug_arch()) {
|
|
case ARM_DEBUG_ARCH_V7_1:
|
|
return true;
|
|
case ARM_DEBUG_ARCH_V7_ECP14:
|
|
ARM_DBG_READ(c1, c1, 4, oslsr);
|
|
if (oslsr & ARM_OSLSR_OSLM0)
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static void reset_ctrl_regs(unsigned int cpu)
|
|
{
|
|
int i, raw_num_brps, err = 0;
|
|
u32 val;
|
|
|
|
/*
|
|
* v7 debug contains save and restore registers so that debug state
|
|
* can be maintained across low-power modes without leaving the debug
|
|
* logic powered up. It is IMPLEMENTATION DEFINED whether we can access
|
|
* the debug registers out of reset, so we must unlock the OS Lock
|
|
* Access Register to avoid taking undefined instruction exceptions
|
|
* later on.
|
|
*/
|
|
switch (debug_arch) {
|
|
case ARM_DEBUG_ARCH_V6:
|
|
case ARM_DEBUG_ARCH_V6_1:
|
|
/* ARMv6 cores clear the registers out of reset. */
|
|
goto out_mdbgen;
|
|
case ARM_DEBUG_ARCH_V7_ECP14:
|
|
/*
|
|
* Ensure sticky power-down is clear (i.e. debug logic is
|
|
* powered up).
|
|
*/
|
|
ARM_DBG_READ(c1, c5, 4, val);
|
|
if ((val & 0x1) == 0)
|
|
err = -EPERM;
|
|
|
|
if (!has_ossr)
|
|
goto clear_vcr;
|
|
break;
|
|
case ARM_DEBUG_ARCH_V7_1:
|
|
/*
|
|
* Ensure the OS double lock is clear.
|
|
*/
|
|
ARM_DBG_READ(c1, c3, 4, val);
|
|
if ((val & 0x1) == 1)
|
|
err = -EPERM;
|
|
break;
|
|
}
|
|
|
|
if (err) {
|
|
pr_warn_once("CPU %d debug is powered down!\n", cpu);
|
|
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Unconditionally clear the OS lock by writing a value
|
|
* other than CS_LAR_KEY to the access register.
|
|
*/
|
|
ARM_DBG_WRITE(c1, c0, 4, ~CORESIGHT_UNLOCK);
|
|
isb();
|
|
|
|
/*
|
|
* Clear any configured vector-catch events before
|
|
* enabling monitor mode.
|
|
*/
|
|
clear_vcr:
|
|
ARM_DBG_WRITE(c0, c7, 0, 0);
|
|
isb();
|
|
|
|
if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
|
|
pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* The control/value register pairs are UNKNOWN out of reset so
|
|
* clear them to avoid spurious debug events.
|
|
*/
|
|
raw_num_brps = get_num_brp_resources();
|
|
for (i = 0; i < raw_num_brps; ++i) {
|
|
write_wb_reg(ARM_BASE_BCR + i, 0UL);
|
|
write_wb_reg(ARM_BASE_BVR + i, 0UL);
|
|
}
|
|
|
|
for (i = 0; i < core_num_wrps; ++i) {
|
|
write_wb_reg(ARM_BASE_WCR + i, 0UL);
|
|
write_wb_reg(ARM_BASE_WVR + i, 0UL);
|
|
}
|
|
|
|
if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
|
|
pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Have a crack at enabling monitor mode. We don't actually need
|
|
* it yet, but reporting an error early is useful if it fails.
|
|
*/
|
|
out_mdbgen:
|
|
if (enable_monitor_mode())
|
|
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
|
|
}
|
|
|
|
static int dbg_reset_online(unsigned int cpu)
|
|
{
|
|
local_irq_disable();
|
|
reset_ctrl_regs(cpu);
|
|
local_irq_enable();
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_PM
|
|
static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
|
|
void *v)
|
|
{
|
|
if (action == CPU_PM_EXIT)
|
|
reset_ctrl_regs(smp_processor_id());
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block dbg_cpu_pm_nb = {
|
|
.notifier_call = dbg_cpu_pm_notify,
|
|
};
|
|
|
|
static void __init pm_init(void)
|
|
{
|
|
cpu_pm_register_notifier(&dbg_cpu_pm_nb);
|
|
}
|
|
#else
|
|
static inline void pm_init(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
static int __init arch_hw_breakpoint_init(void)
|
|
{
|
|
int ret;
|
|
|
|
debug_arch = get_debug_arch();
|
|
|
|
if (!debug_arch_supported()) {
|
|
pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD
|
|
* whenever a WFI is issued, even if the core is not powered down, in
|
|
* violation of the architecture. When DBGPRSR.SPD is set, accesses to
|
|
* breakpoint and watchpoint registers are treated as undefined, so
|
|
* this results in boot time and runtime failures when these are
|
|
* accessed and we unexpectedly take a trap.
|
|
*
|
|
* It's not clear if/how this can be worked around, so we blacklist
|
|
* Scorpion CPUs to avoid these issues.
|
|
*/
|
|
if (read_cpuid_part() == ARM_CPU_PART_SCORPION) {
|
|
pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n");
|
|
return 0;
|
|
}
|
|
|
|
has_ossr = core_has_os_save_restore();
|
|
|
|
/* Determine how many BRPs/WRPs are available. */
|
|
core_num_brps = get_num_brps();
|
|
core_num_wrps = get_num_wrps();
|
|
|
|
/*
|
|
* We need to tread carefully here because DBGSWENABLE may be
|
|
* driven low on this core and there isn't an architected way to
|
|
* determine that.
|
|
*/
|
|
cpus_read_lock();
|
|
register_undef_hook(&debug_reg_hook);
|
|
|
|
/*
|
|
* Register CPU notifier which resets the breakpoint resources. We
|
|
* assume that a halting debugger will leave the world in a nice state
|
|
* for us.
|
|
*/
|
|
ret = cpuhp_setup_state_cpuslocked(CPUHP_AP_ONLINE_DYN,
|
|
"arm/hw_breakpoint:online",
|
|
dbg_reset_online, NULL);
|
|
unregister_undef_hook(&debug_reg_hook);
|
|
if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) {
|
|
core_num_brps = 0;
|
|
core_num_wrps = 0;
|
|
if (ret > 0)
|
|
cpuhp_remove_state_nocalls_cpuslocked(ret);
|
|
cpus_read_unlock();
|
|
return 0;
|
|
}
|
|
|
|
pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
|
|
core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
|
|
"", core_num_wrps);
|
|
|
|
/* Work out the maximum supported watchpoint length. */
|
|
max_watchpoint_len = get_max_wp_len();
|
|
pr_info("maximum watchpoint size is %u bytes.\n",
|
|
max_watchpoint_len);
|
|
|
|
/* Register debug fault handler. */
|
|
hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
|
|
TRAP_HWBKPT, "watchpoint debug exception");
|
|
hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
|
|
TRAP_HWBKPT, "breakpoint debug exception");
|
|
cpus_read_unlock();
|
|
|
|
/* Register PM notifiers. */
|
|
pm_init();
|
|
return 0;
|
|
}
|
|
arch_initcall(arch_hw_breakpoint_init);
|
|
|
|
void hw_breakpoint_pmu_read(struct perf_event *bp)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Dummy function to register with die_notifier.
|
|
*/
|
|
int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
|
|
unsigned long val, void *data)
|
|
{
|
|
return NOTIFY_DONE;
|
|
}
|