892 lines
22 KiB
C
892 lines
22 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/console.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "atom.h"
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/*
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* Clear GPU surface registers.
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*/
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void radeon_surface_init(struct radeon_device *rdev)
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{
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/* FIXME: check this out */
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if (rdev->family < CHIP_R600) {
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int i;
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for (i = 0; i < 8; i++) {
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WREG32(RADEON_SURFACE0_INFO +
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i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
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0);
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}
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/* enable surfaces */
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WREG32(RADEON_SURFACE_CNTL, 0);
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}
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}
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/*
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* GPU scratch registers helpers function.
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*/
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void radeon_scratch_init(struct radeon_device *rdev)
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{
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int i;
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/* FIXME: check this out */
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if (rdev->family < CHIP_R300) {
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rdev->scratch.num_reg = 5;
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} else {
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rdev->scratch.num_reg = 7;
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}
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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rdev->scratch.free[i] = true;
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rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
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}
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}
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.free[i]) {
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rdev->scratch.free[i] = false;
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*reg = rdev->scratch.reg[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.reg[i] == reg) {
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rdev->scratch.free[i] = true;
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return;
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}
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}
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}
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/*
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* MC common functions
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*/
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int radeon_mc_setup(struct radeon_device *rdev)
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{
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uint32_t tmp;
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/* Some chips have an "issue" with the memory controller, the
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* location must be aligned to the size. We just align it down,
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* too bad if we walk over the top of system memory, we don't
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* use DMA without a remapped anyway.
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* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
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*/
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/* FGLRX seems to setup like this, VRAM a 0, then GART.
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*/
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/*
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* Note: from R6xx the address space is 40bits but here we only
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* use 32bits (still have to see a card which would exhaust 4G
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* address space).
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*/
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if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
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/* vram location was already setup try to put gtt after
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* if it fits */
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tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
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tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
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if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
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rdev->mc.gtt_location = tmp;
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} else {
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if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
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printk(KERN_ERR "[drm] GTT too big to fit "
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"before or after vram location.\n");
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return -EINVAL;
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}
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rdev->mc.gtt_location = 0;
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}
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} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
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/* gtt location was already setup try to put vram before
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* if it fits */
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if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
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rdev->mc.vram_location = 0;
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} else {
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tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
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tmp += (rdev->mc.mc_vram_size - 1);
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tmp &= ~(rdev->mc.mc_vram_size - 1);
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if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
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rdev->mc.vram_location = tmp;
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} else {
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printk(KERN_ERR "[drm] vram too big to fit "
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"before or after GTT location.\n");
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return -EINVAL;
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}
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}
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} else {
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rdev->mc.vram_location = 0;
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tmp = rdev->mc.mc_vram_size;
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tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
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rdev->mc.gtt_location = tmp;
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}
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rdev->mc.vram_start = rdev->mc.vram_location;
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rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
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rdev->mc.gtt_start = rdev->mc.gtt_location;
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rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
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DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
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DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
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(unsigned)rdev->mc.vram_location,
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(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
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DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
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DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
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(unsigned)rdev->mc.gtt_location,
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(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
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return 0;
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}
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/*
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* GPU helpers function.
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*/
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bool radeon_card_posted(struct radeon_device *rdev)
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{
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uint32_t reg;
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/* first check CRTCs */
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if (ASIC_IS_AVIVO(rdev)) {
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reg = RREG32(AVIVO_D1CRTC_CONTROL) |
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RREG32(AVIVO_D2CRTC_CONTROL);
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if (reg & AVIVO_CRTC_EN) {
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return true;
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}
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} else {
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reg = RREG32(RADEON_CRTC_GEN_CNTL) |
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RREG32(RADEON_CRTC2_GEN_CNTL);
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if (reg & RADEON_CRTC_EN) {
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return true;
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}
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}
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/* then check MEM_SIZE, in case the crtcs are off */
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if (rdev->family >= CHIP_R600)
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reg = RREG32(R600_CONFIG_MEMSIZE);
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else
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reg = RREG32(RADEON_CONFIG_MEMSIZE);
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if (reg)
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return true;
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return false;
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}
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int radeon_dummy_page_init(struct radeon_device *rdev)
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{
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rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
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if (rdev->dummy_page.page == NULL)
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return -ENOMEM;
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rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
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0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (!rdev->dummy_page.addr) {
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__free_page(rdev->dummy_page.page);
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rdev->dummy_page.page = NULL;
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return -ENOMEM;
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}
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return 0;
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}
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void radeon_dummy_page_fini(struct radeon_device *rdev)
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{
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if (rdev->dummy_page.page == NULL)
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return;
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pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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__free_page(rdev->dummy_page.page);
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rdev->dummy_page.page = NULL;
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}
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/*
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* Registers accessors functions.
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*/
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uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
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BUG_ON(1);
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return 0;
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}
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void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
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reg, v);
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BUG_ON(1);
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}
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void radeon_register_accessor_init(struct radeon_device *rdev)
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{
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rdev->mc_rreg = &radeon_invalid_rreg;
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rdev->mc_wreg = &radeon_invalid_wreg;
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rdev->pll_rreg = &radeon_invalid_rreg;
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rdev->pll_wreg = &radeon_invalid_wreg;
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rdev->pciep_rreg = &radeon_invalid_rreg;
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rdev->pciep_wreg = &radeon_invalid_wreg;
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/* Don't change order as we are overridding accessor. */
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if (rdev->family < CHIP_RV515) {
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rdev->pcie_reg_mask = 0xff;
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} else {
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rdev->pcie_reg_mask = 0x7ff;
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}
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/* FIXME: not sure here */
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if (rdev->family <= CHIP_R580) {
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rdev->pll_rreg = &r100_pll_rreg;
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rdev->pll_wreg = &r100_pll_wreg;
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}
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if (rdev->family >= CHIP_R420) {
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rdev->mc_rreg = &r420_mc_rreg;
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rdev->mc_wreg = &r420_mc_wreg;
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}
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if (rdev->family >= CHIP_RV515) {
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rdev->mc_rreg = &rv515_mc_rreg;
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rdev->mc_wreg = &rv515_mc_wreg;
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}
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
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rdev->mc_rreg = &rs400_mc_rreg;
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rdev->mc_wreg = &rs400_mc_wreg;
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}
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if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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rdev->mc_rreg = &rs690_mc_rreg;
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rdev->mc_wreg = &rs690_mc_wreg;
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}
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if (rdev->family == CHIP_RS600) {
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rdev->mc_rreg = &rs600_mc_rreg;
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rdev->mc_wreg = &rs600_mc_wreg;
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}
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if (rdev->family >= CHIP_R600) {
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rdev->pciep_rreg = &r600_pciep_rreg;
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rdev->pciep_wreg = &r600_pciep_wreg;
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}
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}
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/*
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* ASIC
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*/
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int radeon_asic_init(struct radeon_device *rdev)
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{
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radeon_register_accessor_init(rdev);
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switch (rdev->family) {
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case CHIP_R100:
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case CHIP_RV100:
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case CHIP_RS100:
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case CHIP_RV200:
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case CHIP_RS200:
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case CHIP_R200:
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case CHIP_RV250:
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case CHIP_RS300:
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case CHIP_RV280:
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rdev->asic = &r100_asic;
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break;
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_RV350:
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case CHIP_RV380:
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rdev->asic = &r300_asic;
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if (rdev->flags & RADEON_IS_PCIE) {
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rdev->asic->gart_init = &rv370_pcie_gart_init;
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rdev->asic->gart_fini = &rv370_pcie_gart_fini;
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rdev->asic->gart_enable = &rv370_pcie_gart_enable;
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rdev->asic->gart_disable = &rv370_pcie_gart_disable;
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rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
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rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
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}
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break;
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case CHIP_R420:
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case CHIP_R423:
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case CHIP_RV410:
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rdev->asic = &r420_asic;
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break;
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case CHIP_RS400:
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case CHIP_RS480:
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rdev->asic = &rs400_asic;
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break;
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case CHIP_RS600:
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rdev->asic = &rs600_asic;
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break;
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case CHIP_RS690:
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case CHIP_RS740:
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rdev->asic = &rs690_asic;
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break;
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case CHIP_RV515:
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rdev->asic = &rv515_asic;
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break;
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case CHIP_R520:
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case CHIP_RV530:
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case CHIP_RV560:
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case CHIP_RV570:
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case CHIP_R580:
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rdev->asic = &r520_asic;
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break;
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case CHIP_R600:
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case CHIP_RV610:
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case CHIP_RV630:
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case CHIP_RV620:
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case CHIP_RV635:
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case CHIP_RV670:
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case CHIP_RS780:
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case CHIP_RS880:
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rdev->asic = &r600_asic;
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break;
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case CHIP_RV770:
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case CHIP_RV730:
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case CHIP_RV710:
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case CHIP_RV740:
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rdev->asic = &rv770_asic;
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break;
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default:
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/* FIXME: not supported yet */
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Wrapper around modesetting bits.
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*/
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int radeon_clocks_init(struct radeon_device *rdev)
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{
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int r;
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r = radeon_static_clocks_init(rdev->ddev);
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if (r) {
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return r;
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}
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DRM_INFO("Clocks initialized !\n");
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return 0;
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}
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void radeon_clocks_fini(struct radeon_device *rdev)
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{
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}
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/* ATOM accessor methods */
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static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = rdev->pll_rreg(rdev, reg);
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return r;
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}
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static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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rdev->pll_wreg(rdev, reg, val);
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}
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static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = rdev->mc_rreg(rdev, reg);
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return r;
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}
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static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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rdev->mc_wreg(rdev, reg, val);
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}
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static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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WREG32(reg*4, val);
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}
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static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = RREG32(reg*4);
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return r;
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}
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static struct card_info atom_card_info = {
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.dev = NULL,
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.reg_read = cail_reg_read,
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.reg_write = cail_reg_write,
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.mc_read = cail_mc_read,
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.mc_write = cail_mc_write,
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.pll_read = cail_pll_read,
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.pll_write = cail_pll_write,
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};
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int radeon_atombios_init(struct radeon_device *rdev)
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{
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atom_card_info.dev = rdev->ddev;
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rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
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radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
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return 0;
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}
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void radeon_atombios_fini(struct radeon_device *rdev)
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{
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kfree(rdev->mode_info.atom_context);
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}
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int radeon_combios_init(struct radeon_device *rdev)
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{
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radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
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return 0;
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}
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void radeon_combios_fini(struct radeon_device *rdev)
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{
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}
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/*
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* Radeon device.
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*/
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int radeon_device_init(struct radeon_device *rdev,
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struct drm_device *ddev,
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struct pci_dev *pdev,
|
|
uint32_t flags)
|
|
{
|
|
int r;
|
|
int dma_bits;
|
|
|
|
DRM_INFO("radeon: Initializing kernel modesetting.\n");
|
|
rdev->shutdown = false;
|
|
rdev->dev = &pdev->dev;
|
|
rdev->ddev = ddev;
|
|
rdev->pdev = pdev;
|
|
rdev->flags = flags;
|
|
rdev->family = flags & RADEON_FAMILY_MASK;
|
|
rdev->is_atom_bios = false;
|
|
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
rdev->gpu_lockup = false;
|
|
rdev->accel_working = false;
|
|
/* mutex initialization are all done here so we
|
|
* can recall function without having locking issues */
|
|
mutex_init(&rdev->cs_mutex);
|
|
mutex_init(&rdev->ib_pool.mutex);
|
|
mutex_init(&rdev->cp.mutex);
|
|
rwlock_init(&rdev->fence_drv.lock);
|
|
INIT_LIST_HEAD(&rdev->gem.objects);
|
|
|
|
/* Set asic functions */
|
|
r = radeon_asic_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
if (radeon_agpmode == -1) {
|
|
rdev->flags &= ~RADEON_IS_AGP;
|
|
if (rdev->family >= CHIP_RV515 ||
|
|
rdev->family == CHIP_RV380 ||
|
|
rdev->family == CHIP_RV410 ||
|
|
rdev->family == CHIP_R423) {
|
|
DRM_INFO("Forcing AGP to PCIE mode\n");
|
|
rdev->flags |= RADEON_IS_PCIE;
|
|
rdev->asic->gart_init = &rv370_pcie_gart_init;
|
|
rdev->asic->gart_fini = &rv370_pcie_gart_fini;
|
|
rdev->asic->gart_enable = &rv370_pcie_gart_enable;
|
|
rdev->asic->gart_disable = &rv370_pcie_gart_disable;
|
|
rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
|
|
rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
|
|
} else {
|
|
DRM_INFO("Forcing AGP to PCI mode\n");
|
|
rdev->flags |= RADEON_IS_PCI;
|
|
rdev->asic->gart_init = &r100_pci_gart_init;
|
|
rdev->asic->gart_fini = &r100_pci_gart_fini;
|
|
rdev->asic->gart_enable = &r100_pci_gart_enable;
|
|
rdev->asic->gart_disable = &r100_pci_gart_disable;
|
|
rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
|
|
rdev->asic->gart_set_page = &r100_pci_gart_set_page;
|
|
}
|
|
}
|
|
|
|
/* set DMA mask + need_dma32 flags.
|
|
* PCIE - can handle 40-bits.
|
|
* IGP - can handle 40-bits (in theory)
|
|
* AGP - generally dma32 is safest
|
|
* PCI - only dma32
|
|
*/
|
|
rdev->need_dma32 = false;
|
|
if (rdev->flags & RADEON_IS_AGP)
|
|
rdev->need_dma32 = true;
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
rdev->need_dma32 = true;
|
|
|
|
dma_bits = rdev->need_dma32 ? 32 : 40;
|
|
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
printk(KERN_WARNING "radeon: No suitable DMA available.\n");
|
|
}
|
|
|
|
/* Registers mapping */
|
|
/* TODO: block userspace mapping of io register */
|
|
rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
|
|
rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
|
|
rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
|
|
if (rdev->rmmio == NULL) {
|
|
return -ENOMEM;
|
|
}
|
|
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
|
|
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
|
|
|
|
rdev->new_init_path = false;
|
|
r = radeon_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
if (!rdev->new_init_path) {
|
|
/* Setup errata flags */
|
|
radeon_errata(rdev);
|
|
/* Initialize scratch registers */
|
|
radeon_scratch_init(rdev);
|
|
/* Initialize surface registers */
|
|
radeon_surface_init(rdev);
|
|
|
|
/* TODO: disable VGA need to use VGA request */
|
|
/* BIOS*/
|
|
if (!radeon_get_bios(rdev)) {
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
return -EINVAL;
|
|
}
|
|
if (rdev->is_atom_bios) {
|
|
r = radeon_atombios_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
} else {
|
|
r = radeon_combios_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
}
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
|
if (radeon_gpu_reset(rdev)) {
|
|
/* FIXME: what do we want to do here ? */
|
|
}
|
|
/* check if cards are posted or not */
|
|
if (!radeon_card_posted(rdev) && rdev->bios) {
|
|
DRM_INFO("GPU not posted. posting now...\n");
|
|
if (rdev->is_atom_bios) {
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
} else {
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
}
|
|
}
|
|
/* Get clock & vram information */
|
|
radeon_get_clock_info(rdev->ddev);
|
|
radeon_vram_info(rdev);
|
|
/* Initialize clocks */
|
|
r = radeon_clocks_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
/* Initialize memory controller (also test AGP) */
|
|
r = radeon_mc_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
/* Fence driver */
|
|
r = radeon_fence_driver_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
r = radeon_irq_kms_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
/* Memory manager */
|
|
r = radeon_object_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
r = radeon_gpu_gart_init(rdev);
|
|
if (r)
|
|
return r;
|
|
/* Initialize GART (initialize after TTM so we can allocate
|
|
* memory through TTM but finalize after TTM) */
|
|
r = radeon_gart_enable(rdev);
|
|
if (r)
|
|
return 0;
|
|
r = radeon_gem_init(rdev);
|
|
if (r)
|
|
return 0;
|
|
|
|
/* 1M ring buffer */
|
|
r = radeon_cp_init(rdev, 1024 * 1024);
|
|
if (r)
|
|
return 0;
|
|
r = radeon_wb_init(rdev);
|
|
if (r)
|
|
DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
|
|
r = radeon_ib_pool_init(rdev);
|
|
if (r)
|
|
return 0;
|
|
r = radeon_ib_test(rdev);
|
|
if (r)
|
|
return 0;
|
|
rdev->accel_working = true;
|
|
}
|
|
DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
|
|
if (radeon_testing) {
|
|
radeon_test_moves(rdev);
|
|
}
|
|
if (radeon_benchmarking) {
|
|
radeon_benchmark(rdev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void radeon_device_fini(struct radeon_device *rdev)
|
|
{
|
|
DRM_INFO("radeon: finishing device.\n");
|
|
rdev->shutdown = true;
|
|
/* Order matter so becarefull if you rearrange anythings */
|
|
if (!rdev->new_init_path) {
|
|
radeon_ib_pool_fini(rdev);
|
|
radeon_cp_fini(rdev);
|
|
radeon_wb_fini(rdev);
|
|
radeon_gpu_gart_fini(rdev);
|
|
radeon_gem_fini(rdev);
|
|
radeon_mc_fini(rdev);
|
|
#if __OS_HAS_AGP
|
|
radeon_agp_fini(rdev);
|
|
#endif
|
|
radeon_irq_kms_fini(rdev);
|
|
radeon_fence_driver_fini(rdev);
|
|
radeon_clocks_fini(rdev);
|
|
radeon_object_fini(rdev);
|
|
if (rdev->is_atom_bios) {
|
|
radeon_atombios_fini(rdev);
|
|
} else {
|
|
radeon_combios_fini(rdev);
|
|
}
|
|
kfree(rdev->bios);
|
|
rdev->bios = NULL;
|
|
} else {
|
|
radeon_fini(rdev);
|
|
}
|
|
iounmap(rdev->rmmio);
|
|
rdev->rmmio = NULL;
|
|
}
|
|
|
|
|
|
/*
|
|
* Suspend & resume.
|
|
*/
|
|
int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct drm_crtc *crtc;
|
|
|
|
if (dev == NULL || rdev == NULL) {
|
|
return -ENODEV;
|
|
}
|
|
if (state.event == PM_EVENT_PRETHAW) {
|
|
return 0;
|
|
}
|
|
/* unpin the front buffers */
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
|
struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
|
|
struct radeon_object *robj;
|
|
|
|
if (rfb == NULL || rfb->obj == NULL) {
|
|
continue;
|
|
}
|
|
robj = rfb->obj->driver_private;
|
|
if (robj != rdev->fbdev_robj) {
|
|
radeon_object_unpin(robj);
|
|
}
|
|
}
|
|
/* evict vram memory */
|
|
radeon_object_evict_vram(rdev);
|
|
/* wait for gpu to finish processing current batch */
|
|
radeon_fence_wait_last(rdev);
|
|
|
|
radeon_save_bios_scratch_regs(rdev);
|
|
|
|
if (!rdev->new_init_path) {
|
|
radeon_cp_disable(rdev);
|
|
radeon_gart_disable(rdev);
|
|
rdev->irq.sw_int = false;
|
|
radeon_irq_set(rdev);
|
|
} else {
|
|
radeon_suspend(rdev);
|
|
}
|
|
/* evict remaining vram memory */
|
|
radeon_object_evict_vram(rdev);
|
|
|
|
pci_save_state(dev->pdev);
|
|
if (state.event == PM_EVENT_SUSPEND) {
|
|
/* Shut down the device */
|
|
pci_disable_device(dev->pdev);
|
|
pci_set_power_state(dev->pdev, PCI_D3hot);
|
|
}
|
|
acquire_console_sem();
|
|
fb_set_suspend(rdev->fbdev_info, 1);
|
|
release_console_sem();
|
|
return 0;
|
|
}
|
|
|
|
int radeon_resume_kms(struct drm_device *dev)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
int r;
|
|
|
|
acquire_console_sem();
|
|
pci_set_power_state(dev->pdev, PCI_D0);
|
|
pci_restore_state(dev->pdev);
|
|
if (pci_enable_device(dev->pdev)) {
|
|
release_console_sem();
|
|
return -1;
|
|
}
|
|
pci_set_master(dev->pdev);
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
|
if (!rdev->new_init_path) {
|
|
if (radeon_gpu_reset(rdev)) {
|
|
/* FIXME: what do we want to do here ? */
|
|
}
|
|
/* post card */
|
|
if (rdev->is_atom_bios) {
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
} else {
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
}
|
|
/* Initialize clocks */
|
|
r = radeon_clocks_init(rdev);
|
|
if (r) {
|
|
release_console_sem();
|
|
return r;
|
|
}
|
|
/* Enable IRQ */
|
|
rdev->irq.sw_int = true;
|
|
radeon_irq_set(rdev);
|
|
/* Initialize GPU Memory Controller */
|
|
r = radeon_mc_init(rdev);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
r = radeon_gart_enable(rdev);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
r = radeon_cp_init(rdev, rdev->cp.ring_size);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
} else {
|
|
radeon_resume(rdev);
|
|
}
|
|
out:
|
|
radeon_restore_bios_scratch_regs(rdev);
|
|
fb_set_suspend(rdev->fbdev_info, 0);
|
|
release_console_sem();
|
|
|
|
/* blat the mode back in */
|
|
drm_helper_resume_force_mode(dev);
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Debugfs
|
|
*/
|
|
struct radeon_debugfs {
|
|
struct drm_info_list *files;
|
|
unsigned num_files;
|
|
};
|
|
static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
|
|
static unsigned _radeon_debugfs_count = 0;
|
|
|
|
int radeon_debugfs_add_files(struct radeon_device *rdev,
|
|
struct drm_info_list *files,
|
|
unsigned nfiles)
|
|
{
|
|
unsigned i;
|
|
|
|
for (i = 0; i < _radeon_debugfs_count; i++) {
|
|
if (_radeon_debugfs[i].files == files) {
|
|
/* Already registered */
|
|
return 0;
|
|
}
|
|
}
|
|
if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
|
|
DRM_ERROR("Reached maximum number of debugfs files.\n");
|
|
DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
|
|
return -EINVAL;
|
|
}
|
|
_radeon_debugfs[_radeon_debugfs_count].files = files;
|
|
_radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
|
|
_radeon_debugfs_count++;
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
drm_debugfs_create_files(files, nfiles,
|
|
rdev->ddev->control->debugfs_root,
|
|
rdev->ddev->control);
|
|
drm_debugfs_create_files(files, nfiles,
|
|
rdev->ddev->primary->debugfs_root,
|
|
rdev->ddev->primary);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
int radeon_debugfs_init(struct drm_minor *minor)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void radeon_debugfs_cleanup(struct drm_minor *minor)
|
|
{
|
|
unsigned i;
|
|
|
|
for (i = 0; i < _radeon_debugfs_count; i++) {
|
|
drm_debugfs_remove_files(_radeon_debugfs[i].files,
|
|
_radeon_debugfs[i].num_files, minor);
|
|
}
|
|
}
|
|
#endif
|