402 lines
10 KiB
Plaintext
402 lines
10 KiB
Plaintext
/*
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* dts file for AppliedMicro (APM) X-Gene Storm SOC
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*
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* Copyright (C) 2013, Applied Micro Circuits Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/ {
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compatible = "apm,xgene-storm";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@000 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x000>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@001 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x001>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x201>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x301>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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};
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gic: interrupt-controller@78010000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
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<0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
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<0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
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<0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
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interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
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<1 13 0xff01>, /* Non-secure Phys IRQ */
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<1 14 0xff01>, /* Virt IRQ */
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<1 15 0xff01>; /* Hyp IRQ */
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clock-frequency = <50000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <100000000>;
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clock-output-names = "refclk";
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};
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pcppll: pcppll@17000100 {
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compatible = "apm,xgene-pcppll-clock";
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#clock-cells = <1>;
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clocks = <&refclk 0>;
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clock-names = "pcppll";
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reg = <0x0 0x17000100 0x0 0x1000>;
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clock-output-names = "pcppll";
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type = <0>;
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};
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socpll: socpll@17000120 {
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compatible = "apm,xgene-socpll-clock";
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#clock-cells = <1>;
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clocks = <&refclk 0>;
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clock-names = "socpll";
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reg = <0x0 0x17000120 0x0 0x1000>;
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clock-output-names = "socpll";
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type = <1>;
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};
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socplldiv2: socplldiv2 {
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compatible = "fixed-factor-clock";
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#clock-cells = <1>;
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clocks = <&socpll 0>;
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clock-names = "socplldiv2";
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "socplldiv2";
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};
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qmlclk: qmlclk {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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clock-names = "qmlclk";
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reg = <0x0 0x1703C000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "qmlclk";
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};
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ethclk: ethclk {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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clock-names = "ethclk";
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reg = <0x0 0x17000000 0x0 0x1000>;
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reg-names = "div-reg";
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divider-offset = <0x238>;
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divider-width = <0x9>;
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divider-shift = <0x0>;
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clock-output-names = "ethclk";
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};
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eth8clk: eth8clk {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <ðclk 0>;
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clock-names = "eth8clk";
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reg = <0x0 0x1702C000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "eth8clk";
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};
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sataphy1clk: sataphy1clk@1f21c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f21c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sataphy1clk";
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status = "disabled";
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csr-offset = <0x4>;
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csr-mask = <0x00>;
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enable-offset = <0x0>;
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enable-mask = <0x06>;
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};
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sataphy2clk: sataphy1clk@1f22c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f22c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sataphy2clk";
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status = "ok";
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csr-offset = <0x4>;
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csr-mask = <0x3a>;
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enable-offset = <0x0>;
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enable-mask = <0x06>;
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};
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sataphy3clk: sataphy1clk@1f23c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f23c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sataphy3clk";
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status = "ok";
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csr-offset = <0x4>;
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csr-mask = <0x3a>;
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enable-offset = <0x0>;
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enable-mask = <0x06>;
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};
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sata01clk: sata01clk@1f21c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f21c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sata01clk";
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csr-offset = <0x4>;
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csr-mask = <0x05>;
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enable-offset = <0x0>;
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enable-mask = <0x39>;
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};
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sata23clk: sata23clk@1f22c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f22c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sata23clk";
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csr-offset = <0x4>;
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csr-mask = <0x05>;
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enable-offset = <0x0>;
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enable-mask = <0x39>;
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};
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sata45clk: sata45clk@1f23c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f23c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sata45clk";
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csr-offset = <0x4>;
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csr-mask = <0x05>;
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enable-offset = <0x0>;
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enable-mask = <0x39>;
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};
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rtcclk: rtcclk@17000000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x17000000 0x0 0x2000>;
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reg-names = "csr-reg";
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csr-offset = <0xc>;
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csr-mask = <0x2>;
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enable-offset = <0x10>;
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enable-mask = <0x2>;
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clock-output-names = "rtcclk";
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};
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};
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serial0: serial@1c020000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0 0x1c020000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4c 0x4>;
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};
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serial1: serial@1c021000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0 0x1c021000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4d 0x4>;
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};
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serial2: serial@1c022000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0 0x1c022000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4e 0x4>;
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};
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serial3: serial@1c023000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0 0x1c023000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4f 0x4>;
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};
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phy1: phy@1f21a000 {
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compatible = "apm,xgene-phy";
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reg = <0x0 0x1f21a000 0x0 0x100>;
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#phy-cells = <1>;
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clocks = <&sataphy1clk 0>;
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status = "disabled";
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apm,tx-boost-gain = <30 30 30 30 30 30>;
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apm,tx-eye-tuning = <2 10 10 2 10 10>;
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};
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phy2: phy@1f22a000 {
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compatible = "apm,xgene-phy";
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reg = <0x0 0x1f22a000 0x0 0x100>;
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#phy-cells = <1>;
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clocks = <&sataphy2clk 0>;
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status = "ok";
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apm,tx-boost-gain = <30 30 30 30 30 30>;
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apm,tx-eye-tuning = <1 10 10 2 10 10>;
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};
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phy3: phy@1f23a000 {
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compatible = "apm,xgene-phy";
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reg = <0x0 0x1f23a000 0x0 0x100>;
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#phy-cells = <1>;
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clocks = <&sataphy3clk 0>;
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status = "ok";
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apm,tx-boost-gain = <31 31 31 31 31 31>;
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apm,tx-eye-tuning = <2 10 10 2 10 10>;
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};
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sata1: sata@1a000000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a000000 0x0 0x1000>,
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<0x0 0x1f210000 0x0 0x1000>,
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<0x0 0x1f21d000 0x0 0x1000>,
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<0x0 0x1f21e000 0x0 0x1000>,
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<0x0 0x1f217000 0x0 0x1000>;
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interrupts = <0x0 0x86 0x4>;
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dma-coherent;
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status = "disabled";
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clocks = <&sata01clk 0>;
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phys = <&phy1 0>;
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phy-names = "sata-phy";
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};
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sata2: sata@1a400000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a400000 0x0 0x1000>,
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<0x0 0x1f220000 0x0 0x1000>,
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<0x0 0x1f22d000 0x0 0x1000>,
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<0x0 0x1f22e000 0x0 0x1000>,
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<0x0 0x1f227000 0x0 0x1000>;
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interrupts = <0x0 0x87 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sata23clk 0>;
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phys = <&phy2 0>;
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phy-names = "sata-phy";
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};
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sata3: sata@1a800000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a800000 0x0 0x1000>,
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<0x0 0x1f230000 0x0 0x1000>,
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<0x0 0x1f23d000 0x0 0x1000>,
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<0x0 0x1f23e000 0x0 0x1000>;
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interrupts = <0x0 0x88 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sata45clk 0>;
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phys = <&phy3 0>;
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phy-names = "sata-phy";
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};
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rtc: rtc@10510000 {
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compatible = "apm,xgene-rtc";
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reg = <0x0 0x10510000 0x0 0x400>;
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interrupts = <0x0 0x46 0x4>;
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#clock-cells = <1>;
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clocks = <&rtcclk 0>;
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};
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};
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};
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