176 lines
6.1 KiB
C
176 lines
6.1 KiB
C
/*
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* This file is part of the Chelsio FCoE driver for Linux.
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*
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* Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __CSIO_HW_CHIP_H__
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#define __CSIO_HW_CHIP_H__
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#include "csio_defs.h"
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/* FCoE device IDs for T4 */
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#define CSIO_DEVID_T440DBG_FCOE 0x4600
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#define CSIO_DEVID_T420CR_FCOE 0x4601
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#define CSIO_DEVID_T422CR_FCOE 0x4602
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#define CSIO_DEVID_T440CR_FCOE 0x4603
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#define CSIO_DEVID_T420BCH_FCOE 0x4604
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#define CSIO_DEVID_T440BCH_FCOE 0x4605
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#define CSIO_DEVID_T440CH_FCOE 0x4606
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#define CSIO_DEVID_T420SO_FCOE 0x4607
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#define CSIO_DEVID_T420CX_FCOE 0x4608
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#define CSIO_DEVID_T420BT_FCOE 0x4609
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#define CSIO_DEVID_T404BT_FCOE 0x460A
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#define CSIO_DEVID_B420_FCOE 0x460B
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#define CSIO_DEVID_B404_FCOE 0x460C
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#define CSIO_DEVID_T480CR_FCOE 0x460D
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#define CSIO_DEVID_T440LPCR_FCOE 0x460E
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#define CSIO_DEVID_AMSTERDAM_T4_FCOE 0x460F
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#define CSIO_DEVID_HUAWEI_T480_FCOE 0x4680
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#define CSIO_DEVID_HUAWEI_T440_FCOE 0x4681
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#define CSIO_DEVID_HUAWEI_STG310_FCOE 0x4682
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#define CSIO_DEVID_ACROMAG_XMC_XAUI 0x4683
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#define CSIO_DEVID_ACROMAG_XMC_SFP_FCOE 0x4684
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#define CSIO_DEVID_QUANTA_MEZZ_SFP_FCOE 0x4685
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#define CSIO_DEVID_HUAWEI_10GT_FCOE 0x4686
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#define CSIO_DEVID_HUAWEI_T440_TOE_FCOE 0x4687
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/* FCoE device IDs for T5 */
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#define CSIO_DEVID_T580DBG_FCOE 0x5600
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#define CSIO_DEVID_T520CR_FCOE 0x5601
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#define CSIO_DEVID_T522CR_FCOE 0x5602
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#define CSIO_DEVID_T540CR_FCOE 0x5603
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#define CSIO_DEVID_T520BCH_FCOE 0x5604
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#define CSIO_DEVID_T540BCH_FCOE 0x5605
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#define CSIO_DEVID_T540CH_FCOE 0x5606
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#define CSIO_DEVID_T520SO_FCOE 0x5607
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#define CSIO_DEVID_T520CX_FCOE 0x5608
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#define CSIO_DEVID_T520BT_FCOE 0x5609
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#define CSIO_DEVID_T504BT_FCOE 0x560A
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#define CSIO_DEVID_B520_FCOE 0x560B
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#define CSIO_DEVID_B504_FCOE 0x560C
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#define CSIO_DEVID_T580CR2_FCOE 0x560D
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#define CSIO_DEVID_T540LPCR_FCOE 0x560E
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#define CSIO_DEVID_AMSTERDAM_T5_FCOE 0x560F
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#define CSIO_DEVID_T580LPCR_FCOE 0x5610
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#define CSIO_DEVID_T520LLCR_FCOE 0x5611
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#define CSIO_DEVID_T560CR_FCOE 0x5612
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#define CSIO_DEVID_T580CR_FCOE 0x5613
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/* Define MACRO values */
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#define CSIO_HW_T4 0x4000
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#define CSIO_T4_FCOE_ASIC 0x4600
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#define CSIO_HW_T5 0x5000
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#define CSIO_T5_FCOE_ASIC 0x5600
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#define CSIO_HW_CHIP_MASK 0xF000
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#define T4_REGMAP_SIZE (160 * 1024)
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#define T5_REGMAP_SIZE (332 * 1024)
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#define FW_FNAME_T4 "cxgb4/t4fw.bin"
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#define FW_FNAME_T5 "cxgb4/t5fw.bin"
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#define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
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#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
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/* Define static functions */
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static inline int csio_is_t4(uint16_t chip)
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{
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return (chip == CSIO_HW_T4);
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}
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static inline int csio_is_t5(uint16_t chip)
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{
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return (chip == CSIO_HW_T5);
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}
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/* Define MACRO DEFINITIONS */
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#define CSIO_DEVICE(devid, idx) \
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{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
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#define CSIO_HW_PIDX(hw, index) \
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(csio_is_t4(hw->chip_id) ? (PIDX(index)) : \
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(PIDX_T5(index) | DBTYPE(1U)))
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#define CSIO_HW_LP_INT_THRESH(hw, val) \
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(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) : \
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(V_LP_INT_THRESH_T5(val)))
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#define CSIO_HW_M_LP_INT_THRESH(hw) \
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(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5))
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#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
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(csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
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(T5_PORT_REG(port, MAC_PORT_INT_CAUSE)))
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#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
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#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
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#define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0)
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#define CSIO_FW_FNAME(hw) \
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(csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
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#define CSIO_CF_FNAME(hw) \
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(csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
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/* Declare ENUMS */
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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enum {
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MEMWIN_APERTURE = 2048,
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MEMWIN_BASE = 0x1b800,
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MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
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};
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/* Slow path handlers */
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struct intr_info {
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unsigned int mask; /* bits to check in interrupt status */
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const char *msg; /* message to print or NULL */
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short stat_idx; /* stat counter to increment or -1 */
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unsigned short fatal; /* whether the condition reported is fatal */
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};
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/* T4/T5 Chip specific ops */
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struct csio_hw;
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struct csio_hw_chip_ops {
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int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
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void (*chip_pcie_intr_handler)(struct csio_hw *);
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uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
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int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
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__be32 *, uint64_t *);
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int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
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__be32 *, uint64_t *);
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int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
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u32, uint32_t *, int);
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void (*chip_dfs_create_ext_mem)(struct csio_hw *);
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};
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extern struct csio_hw_chip_ops t4_ops;
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extern struct csio_hw_chip_ops t5_ops;
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#endif /* #ifndef __CSIO_HW_CHIP_H__ */
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