314 lines
8.2 KiB
C
314 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Mediatek SoCs General-Purpose Timer handling.
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*
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* Copyright (C) 2014 Matthias Brugger
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*
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* Matthias Brugger <matthias.bgg@gmail.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include "timer-of.h"
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#define TIMER_CLK_EVT (1)
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#define TIMER_CLK_SRC (2)
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#define TIMER_SYNC_TICKS (3)
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/* gpt */
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#define GPT_IRQ_EN_REG 0x00
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#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
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#define GPT_IRQ_ACK_REG 0x08
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#define GPT_IRQ_ACK(val) BIT((val) - 1)
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#define GPT_CTRL_REG(val) (0x10 * (val))
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#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
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#define GPT_CTRL_OP_ONESHOT (0)
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#define GPT_CTRL_OP_REPEAT (1)
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#define GPT_CTRL_OP_FREERUN (3)
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#define GPT_CTRL_CLEAR (2)
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#define GPT_CTRL_ENABLE (1)
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#define GPT_CTRL_DISABLE (0)
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#define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
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#define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
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#define GPT_CLK_SRC_SYS13M (0)
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#define GPT_CLK_SRC_RTC32K (1)
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#define GPT_CLK_DIV1 (0x0)
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#define GPT_CLK_DIV2 (0x1)
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#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
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#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
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/* system timer */
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#define SYST_BASE (0x40)
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#define SYST_CON (SYST_BASE + 0x0)
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#define SYST_VAL (SYST_BASE + 0x4)
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#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
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#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
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/*
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* SYST_CON_EN: Clock enable. Shall be set to
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* - Start timer countdown.
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* - Allow timeout ticks being updated.
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* - Allow changing interrupt functions.
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*
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* SYST_CON_IRQ_EN: Set to allow interrupt.
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*
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* SYST_CON_IRQ_CLR: Set to clear interrupt.
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*/
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#define SYST_CON_EN BIT(0)
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#define SYST_CON_IRQ_EN BIT(1)
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#define SYST_CON_IRQ_CLR BIT(4)
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static void __iomem *gpt_sched_reg __read_mostly;
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static void mtk_syst_ack_irq(struct timer_of *to)
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{
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/* Clear and disable interrupt */
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writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
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}
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static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
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{
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struct clock_event_device *clkevt = dev_id;
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struct timer_of *to = to_timer_of(clkevt);
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mtk_syst_ack_irq(to);
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clkevt->event_handler(clkevt);
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return IRQ_HANDLED;
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}
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static int mtk_syst_clkevt_next_event(unsigned long ticks,
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struct clock_event_device *clkevt)
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{
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struct timer_of *to = to_timer_of(clkevt);
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/* Enable clock to allow timeout tick update later */
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writel(SYST_CON_EN, SYST_CON_REG(to));
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/*
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* Write new timeout ticks. Timer shall start countdown
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* after timeout ticks are updated.
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*/
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writel(ticks, SYST_VAL_REG(to));
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/* Enable interrupt */
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writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
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return 0;
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}
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static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
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{
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/* Disable timer */
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writel(0, SYST_CON_REG(to_timer_of(clkevt)));
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return 0;
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}
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static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
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{
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return mtk_syst_clkevt_shutdown(clkevt);
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}
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static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
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{
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return 0;
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}
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static u64 notrace mtk_gpt_read_sched_clock(void)
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{
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return readl_relaxed(gpt_sched_reg);
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}
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static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
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{
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u32 val;
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val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
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writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
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GPT_CTRL_REG(timer));
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}
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static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
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unsigned long delay, u8 timer)
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{
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writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
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}
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static void mtk_gpt_clkevt_time_start(struct timer_of *to,
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bool periodic, u8 timer)
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{
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u32 val;
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/* Acknowledge interrupt */
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writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
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val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
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/* Clear 2 bit timer operation mode field */
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val &= ~GPT_CTRL_OP(0x3);
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if (periodic)
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val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
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else
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val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
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writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
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timer_of_base(to) + GPT_CTRL_REG(timer));
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}
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static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
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{
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mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
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return 0;
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}
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static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
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return 0;
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}
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static int mtk_gpt_clkevt_next_event(unsigned long event,
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struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
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return 0;
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}
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static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(clkevt);
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/* Acknowledge timer0 irq */
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writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
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clkevt->event_handler(clkevt);
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return IRQ_HANDLED;
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}
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static void
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__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
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{
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writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
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timer_of_base(to) + GPT_CTRL_REG(timer));
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writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
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timer_of_base(to) + GPT_CLK_REG(timer));
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writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
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writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
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timer_of_base(to) + GPT_CTRL_REG(timer));
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}
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static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
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{
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u32 val;
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/* Disable all interrupts */
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writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
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/* Acknowledge all spurious pending interrupts */
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writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
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val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
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writel(val | GPT_IRQ_ENABLE(timer),
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timer_of_base(to) + GPT_IRQ_EN_REG);
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}
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static struct timer_of to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "mtk-clkevt",
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.rating = 300,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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};
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static int __init mtk_syst_init(struct device_node *node)
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{
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int ret;
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to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
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to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
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to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
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to.clkevt.tick_resume = mtk_syst_clkevt_resume;
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to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
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to.of_irq.handler = mtk_syst_handler;
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ret = timer_of_init(node, &to);
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if (ret)
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return ret;
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
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TIMER_SYNC_TICKS, 0xffffffff);
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return 0;
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}
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static int __init mtk_gpt_init(struct device_node *node)
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{
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int ret;
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to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
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to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
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to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
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to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
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to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
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to.of_irq.handler = mtk_gpt_interrupt;
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ret = timer_of_init(node, &to);
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if (ret)
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return ret;
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/* Configure clock source */
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mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
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clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
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node->name, timer_of_rate(&to), 300, 32,
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clocksource_mmio_readl_up);
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gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
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sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
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/* Configure clock event */
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mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
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TIMER_SYNC_TICKS, 0xffffffff);
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mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
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return 0;
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}
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TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
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TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
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