113 lines
4.0 KiB
C
113 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static const struct flash_info winbond_parts[] = {
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/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
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{ "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
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{ "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
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{ "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
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{ "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
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{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
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{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
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{ "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
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{ "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
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SPI_NOR_HAS_TB) },
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{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
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{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
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{ "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
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{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
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{ "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{ "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
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{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
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{ "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
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{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
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{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
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{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
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};
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/**
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* winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
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* address mode.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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{
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int ret;
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ret = spi_nor_set_4byte_addr_mode(nor, enable);
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if (ret || enable)
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return ret;
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/*
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* On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
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* Register to be set to 1, so all 3-byte-address reads come from the
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* second 16M. We must clear the register to enable normal behavior.
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*/
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ret = spi_nor_write_enable(nor);
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if (ret)
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return ret;
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ret = spi_nor_write_ear(nor, 0);
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if (ret)
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return ret;
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return spi_nor_write_disable(nor);
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}
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static void winbond_default_init(struct spi_nor *nor)
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{
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nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode;
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}
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static const struct spi_nor_fixups winbond_fixups = {
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.default_init = winbond_default_init,
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};
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const struct spi_nor_manufacturer spi_nor_winbond = {
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.name = "winbond",
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.parts = winbond_parts,
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.nparts = ARRAY_SIZE(winbond_parts),
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.fixups = &winbond_fixups,
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};
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