298 lines
8.4 KiB
C
298 lines
8.4 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#include "ixgbe.h"
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82598.h"
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/**
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* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Rx Data Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *prio_type)
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{
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u32 reg = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u8 i = 0;
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reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
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IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
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/* Enable Arbiter */
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reg &= ~IXGBE_RMCS_ARBDIS;
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/* Enable Receive Recycle within the BWG */
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reg |= IXGBE_RMCS_RRM;
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/* Enable Deficit Fixed Priority arbitration*/
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reg |= IXGBE_RMCS_DFP;
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IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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credit_refill = refill[i];
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credit_max = max[i];
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reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RT2CR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
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}
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reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
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reg |= IXGBE_RDRXCTL_RDMTS_1_2;
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reg |= IXGBE_RDRXCTL_MPBEN;
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reg |= IXGBE_RDRXCTL_MCEN;
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IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
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/* Make sure there is enough descriptors before arbitration */
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reg &= ~IXGBE_RXCTRL_DMBYPS;
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IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Tx Descriptor Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type)
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{
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u32 reg, max_credits;
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u8 i;
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reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
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/* Enable arbiter */
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reg &= ~IXGBE_DPMCS_ARBDIS;
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/* Enable DFP and Recycle mode */
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reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
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reg |= IXGBE_DPMCS_TSOEF;
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/* Configure Max TSO packet size 34KB including payload and headers */
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reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
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IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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max_credits = max[i];
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reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
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reg |= refill[i];
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reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_TDTQ2TCCR_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_TDTQ2TCCR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Tx Data Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type)
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{
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u32 reg;
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u8 i;
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reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
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/* Enable Data Plane Arbiter */
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reg &= ~IXGBE_PDPMCS_ARBDIS;
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/* Enable DFP and Transmit Recycle Mode */
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reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
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IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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reg = refill[i];
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reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
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reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_TDPT2TCCR_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_TDPT2TCCR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
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}
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/* Enable Tx packet buffer division */
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reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
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reg |= IXGBE_DTXCTL_ENDBUBD;
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IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_pfc_82598 - Config priority flow control
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Priority Flow Control for each traffic class.
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*/
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s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
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{
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u32 reg, rx_pba_size;
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u8 i;
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if (pfc_en) {
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/* Enable Transmit Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
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reg &= ~IXGBE_RMCS_TFCE_802_3X;
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/* correct the reporting of our flow control status */
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reg |= IXGBE_RMCS_TFCE_PRIORITY;
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IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
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/* Enable Receive Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
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reg &= ~IXGBE_FCTRL_RFCE;
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reg |= IXGBE_FCTRL_RPFCE;
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IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
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/* Configure pause time */
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for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
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/* Configure flow control refresh threshold value */
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
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}
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/*
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* Configure flow control thresholds and enable priority flow control
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* for each traffic class.
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*/
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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int enabled = pfc_en & (1 << i);
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rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
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rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
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reg = (rx_pba_size - hw->fc.low_water) << 10;
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if (enabled == pfc_enabled_tx ||
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enabled == pfc_enabled_full)
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reg |= IXGBE_FCRTL_XONE;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
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reg = (rx_pba_size - hw->fc.high_water) << 10;
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if (enabled == pfc_enabled_tx ||
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enabled == pfc_enabled_full)
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reg |= IXGBE_FCRTH_FCEN;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
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* @hw: pointer to hardware structure
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*
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* Configure queue statistics registers, all queues belonging to same traffic
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* class uses a single set of queue statistics counters.
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*/
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static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
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{
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u32 reg = 0;
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u8 i = 0;
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u8 j = 0;
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/* Receive Queues stats setting - 8 queues per statistics reg */
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for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
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reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
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reg |= ((0x1010101) * j);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
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reg |= ((0x1010101) * j);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
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}
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/* Transmit Queues stats setting - 4 queues per statistics reg */
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for (i = 0; i < 8; i++) {
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reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
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reg |= ((0x1010101) * i);
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IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_hw_config_82598 - Config and enable DCB
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure dcb settings and enable dcb mode.
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*/
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s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type)
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{
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ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
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ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_pfc_82598(hw, pfc_en);
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ixgbe_dcb_config_tc_stats_82598(hw);
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return 0;
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}
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