284 lines
7.8 KiB
C
284 lines
7.8 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#ifndef __NOUVEAU_PM_H__
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#define __NOUVEAU_PM_H__
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#include <subdev/bios/pll.h>
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#include <subdev/clock.h>
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struct nouveau_pm_voltage_level {
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u32 voltage; /* microvolts */
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u8 vid;
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};
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struct nouveau_pm_voltage {
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bool supported;
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u8 version;
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u8 vid_mask;
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struct nouveau_pm_voltage_level *level;
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int nr_level;
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};
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/* Exclusive upper limits */
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#define NV_MEM_CL_DDR2_MAX 8
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#define NV_MEM_WR_DDR2_MAX 9
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#define NV_MEM_CL_DDR3_MAX 17
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#define NV_MEM_WR_DDR3_MAX 17
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#define NV_MEM_CL_GDDR3_MAX 16
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#define NV_MEM_WR_GDDR3_MAX 18
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#define NV_MEM_CL_GDDR5_MAX 21
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#define NV_MEM_WR_GDDR5_MAX 20
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struct nouveau_pm_memtiming {
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int id;
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u32 reg[9];
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u32 mr[4];
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u8 tCWL;
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u8 odt;
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u8 drive_strength;
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};
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struct nouveau_pm_tbl_header {
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u8 version;
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u8 header_len;
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u8 entry_cnt;
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u8 entry_len;
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};
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struct nouveau_pm_tbl_entry {
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u8 tWR;
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u8 tWTR;
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u8 tCL;
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u8 tRC;
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u8 empty_4;
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u8 tRFC; /* Byte 5 */
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u8 empty_6;
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u8 tRAS; /* Byte 7 */
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u8 empty_8;
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u8 tRP; /* Byte 9 */
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u8 tRCDRD;
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u8 tRCDWR;
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u8 tRRD;
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u8 tUNK_13;
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u8 RAM_FT1; /* 14, a bitmask of random RAM features */
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u8 empty_15;
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u8 tUNK_16;
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u8 empty_17;
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u8 tUNK_18;
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u8 tCWL;
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u8 tUNK_20, tUNK_21;
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};
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struct nouveau_pm_profile;
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struct nouveau_pm_profile_func {
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void (*destroy)(struct nouveau_pm_profile *);
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void (*init)(struct nouveau_pm_profile *);
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void (*fini)(struct nouveau_pm_profile *);
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struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
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};
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struct nouveau_pm_profile {
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const struct nouveau_pm_profile_func *func;
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struct list_head head;
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char name[8];
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};
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#define NOUVEAU_PM_MAX_LEVEL 8
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struct nouveau_pm_level {
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struct nouveau_pm_profile profile;
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struct device_attribute dev_attr;
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char name[32];
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int id;
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struct nouveau_pm_memtiming timing;
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u32 memory;
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u16 memscript;
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u32 core;
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u32 shader;
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u32 rop;
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u32 copy;
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u32 daemon;
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u32 vdec;
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u32 dom6;
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u32 unka0; /* nva3:nvc0 */
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u32 hub01; /* nvc0- */
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u32 hub06; /* nvc0- */
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u32 hub07; /* nvc0- */
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u32 volt_min; /* microvolts */
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u32 volt_max;
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u8 fanspeed;
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};
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struct nouveau_pm_temp_sensor_constants {
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u16 offset_constant;
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s16 offset_mult;
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s16 offset_div;
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s16 slope_mult;
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s16 slope_div;
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};
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struct nouveau_pm_threshold_temp {
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s16 critical;
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s16 down_clock;
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};
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struct nouveau_pm {
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struct drm_device *dev;
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struct nouveau_pm_voltage voltage;
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struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
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int nr_perflvl;
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struct nouveau_pm_temp_sensor_constants sensor_constants;
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struct nouveau_pm_threshold_temp threshold_temp;
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struct nouveau_pm_profile *profile_ac;
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struct nouveau_pm_profile *profile_dc;
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struct nouveau_pm_profile *profile;
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struct list_head profiles;
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struct nouveau_pm_level boot;
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struct nouveau_pm_level *cur;
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struct device *hwmon;
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struct notifier_block acpi_nb;
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int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
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void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
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int (*clocks_set)(struct drm_device *, void *);
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int (*voltage_get)(struct drm_device *);
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int (*voltage_set)(struct drm_device *, int voltage);
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};
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static inline struct nouveau_pm *
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nouveau_pm(struct drm_device *dev)
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{
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return nouveau_drm(dev)->pm;
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}
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struct nouveau_mem_exec_func {
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struct drm_device *dev;
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void (*precharge)(struct nouveau_mem_exec_func *);
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void (*refresh)(struct nouveau_mem_exec_func *);
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void (*refresh_auto)(struct nouveau_mem_exec_func *, bool);
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void (*refresh_self)(struct nouveau_mem_exec_func *, bool);
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void (*wait)(struct nouveau_mem_exec_func *, u32 nsec);
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u32 (*mrg)(struct nouveau_mem_exec_func *, int mr);
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void (*mrs)(struct nouveau_mem_exec_func *, int mr, u32 data);
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void (*clock_set)(struct nouveau_mem_exec_func *);
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void (*timing_set)(struct nouveau_mem_exec_func *);
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void *priv;
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};
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/* nouveau_mem.c */
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int nouveau_mem_exec(struct nouveau_mem_exec_func *,
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struct nouveau_pm_level *);
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/* nouveau_pm.c */
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int nouveau_pm_init(struct drm_device *dev);
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void nouveau_pm_fini(struct drm_device *dev);
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void nouveau_pm_resume(struct drm_device *dev);
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extern const struct nouveau_pm_profile_func nouveau_pm_static_profile_func;
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void nouveau_pm_trigger(struct drm_device *dev);
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/* nouveau_volt.c */
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void nouveau_volt_init(struct drm_device *);
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void nouveau_volt_fini(struct drm_device *);
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int nouveau_volt_vid_lookup(struct drm_device *, int voltage);
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int nouveau_volt_lvl_lookup(struct drm_device *, int vid);
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int nouveau_voltage_gpio_get(struct drm_device *);
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int nouveau_voltage_gpio_set(struct drm_device *, int voltage);
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/* nouveau_perf.c */
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void nouveau_perf_init(struct drm_device *);
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void nouveau_perf_fini(struct drm_device *);
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u8 *nouveau_perf_rammap(struct drm_device *, u32 freq, u8 *ver,
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u8 *hdr, u8 *cnt, u8 *len);
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u8 *nouveau_perf_ramcfg(struct drm_device *, u32 freq, u8 *ver, u8 *len);
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u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
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/* nouveau_mem.c */
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void nouveau_mem_timing_init(struct drm_device *);
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void nouveau_mem_timing_fini(struct drm_device *);
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/* nv04_pm.c */
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int nv04_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nv04_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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int nv04_pm_clocks_set(struct drm_device *, void *);
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/* nv40_pm.c */
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int nv40_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nv40_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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int nv40_pm_clocks_set(struct drm_device *, void *);
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int nv40_pm_pwm_get(struct drm_device *, int, u32 *, u32 *);
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int nv40_pm_pwm_set(struct drm_device *, int, u32, u32);
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/* nv50_pm.c */
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int nv50_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nv50_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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int nv50_pm_clocks_set(struct drm_device *, void *);
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int nv50_pm_pwm_get(struct drm_device *, int, u32 *, u32 *);
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int nv50_pm_pwm_set(struct drm_device *, int, u32, u32);
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/* nva3_pm.c */
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int nva3_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nva3_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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int nva3_pm_clocks_set(struct drm_device *, void *);
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/* nvc0_pm.c */
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int nvc0_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nvc0_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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int nvc0_pm_clocks_set(struct drm_device *, void *);
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/* nouveau_mem.c */
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int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
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struct nouveau_pm_memtiming *);
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void nouveau_mem_timing_read(struct drm_device *,
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struct nouveau_pm_memtiming *);
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static inline int
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nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *pll, u32 freq,
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int *N, int *fN, int *M, int *P)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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struct nouveau_clock *clk = nouveau_clock(device);
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struct nouveau_pll_vals pv;
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int ret;
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ret = clk->pll_calc(clk, pll, freq, &pv);
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*N = pv.N1;
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*M = pv.M1;
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*P = pv.log2P;
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return ret;
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}
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#endif
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