526 lines
18 KiB
C
526 lines
18 KiB
C
#ifndef __SOUND_ICE1712_H
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#define __SOUND_ICE1712_H
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/*
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* ALSA driver for ICEnsemble ICE1712 (Envy24)
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*
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* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <sound/control.h>
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#include <sound/ac97_codec.h>
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#include <sound/rawmidi.h>
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#include <sound/i2c.h>
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#include <sound/ak4xxx-adda.h>
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#include <sound/ak4114.h>
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#include <sound/pt2258.h>
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#include <sound/pcm.h>
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#include <sound/mpu401.h>
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/*
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* Direct registers
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*/
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#define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
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#define ICE1712_REG_CONTROL 0x00 /* byte */
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#define ICE1712_RESET 0x80 /* reset whole chip */
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#define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */
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#define ICE1712_NATIVE 0x01 /* native mode otherwise SB */
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#define ICE1712_REG_IRQMASK 0x01 /* byte */
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#define ICE1712_IRQ_MPU1 0x80
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#define ICE1712_IRQ_TIMER 0x40
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#define ICE1712_IRQ_MPU2 0x20
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#define ICE1712_IRQ_PROPCM 0x10
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#define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */
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#define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */
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#define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */
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#define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */
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#define ICE1712_REG_IRQSTAT 0x02 /* byte */
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/* look to ICE1712_IRQ_* */
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#define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */
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#define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */
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#define ICE1712_REG_NMI_STAT1 0x05 /* byte */
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#define ICE1712_REG_NMI_DATA 0x06 /* byte */
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#define ICE1712_REG_NMI_INDEX 0x07 /* byte */
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#define ICE1712_REG_AC97_INDEX 0x08 /* byte */
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#define ICE1712_REG_AC97_CMD 0x09 /* byte */
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#define ICE1712_AC97_COLD 0x80 /* cold reset */
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#define ICE1712_AC97_WARM 0x40 /* warm reset */
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#define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */
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#define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */
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#define ICE1712_AC97_READY 0x08 /* codec ready status bit */
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#define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */
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#define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */
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#define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */
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#define ICE1712_REG_MPU1_CTRL 0x0c /* byte */
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#define ICE1712_REG_MPU1_DATA 0x0d /* byte */
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#define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */
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#define ICE1712_I2C_WRITE 0x01 /* write direction */
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#define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */
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#define ICE1712_REG_I2C_DATA 0x12 /* byte */
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#define ICE1712_REG_I2C_CTRL 0x13 /* byte */
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#define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */
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#define ICE1712_I2C_BUSY 0x01 /* busy bit */
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#define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */
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#define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */
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#define ICE1712_REG_SERR_SHADOW 0x1b /* byte */
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#define ICE1712_REG_MPU2_CTRL 0x1c /* byte */
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#define ICE1712_REG_MPU2_DATA 0x1d /* byte */
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#define ICE1712_REG_TIMER 0x1e /* word */
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/*
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* Indirect registers
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*/
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#define ICE1712_IREG_PBK_COUNT_LO 0x00
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#define ICE1712_IREG_PBK_COUNT_HI 0x01
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#define ICE1712_IREG_PBK_CTRL 0x02
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#define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */
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#define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */
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#define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */
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#define ICE1712_IREG_PBK_RATE_LO 0x06
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#define ICE1712_IREG_PBK_RATE_MID 0x07
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#define ICE1712_IREG_PBK_RATE_HI 0x08
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#define ICE1712_IREG_CAP_COUNT_LO 0x10
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#define ICE1712_IREG_CAP_COUNT_HI 0x11
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#define ICE1712_IREG_CAP_CTRL 0x12
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#define ICE1712_IREG_GPIO_DATA 0x20
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#define ICE1712_IREG_GPIO_WRITE_MASK 0x21
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#define ICE1712_IREG_GPIO_DIRECTION 0x22
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#define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
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#define ICE1712_IREG_PRO_POWERDOWN 0x31
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/*
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* Consumer section direct DMA registers
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*/
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#define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
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#define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */
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#define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */
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#define ICE1712_DS_DATA 0x04 /* dword - channel data */
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#define ICE1712_DS_INDEX 0x08 /* dword - channel index */
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/*
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* Consumer section channel registers
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*/
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#define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */
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#define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */
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#define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */
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#define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */
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#define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */
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#define ICE1712_BUFFER1 0x80 /* buffer1 is active */
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#define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */
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#define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */
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#define ICE1712_FLUSH 0x10 /* flush FIFO */
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#define ICE1712_STEREO 0x08 /* stereo */
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#define ICE1712_16BIT 0x04 /* 16-bit data */
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#define ICE1712_PAUSE 0x02 /* pause */
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#define ICE1712_START 0x01 /* start */
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#define ICE1712_DSC_RATE 0x05 /* dword - rate */
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#define ICE1712_DSC_VOLUME 0x06 /* word - volume control */
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/*
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* Professional multi-track direct control registers
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*/
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#define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
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#define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */
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#define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */
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#define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */
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#define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */
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#define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */
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#define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */
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#define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
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#define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
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#define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
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#define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
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/* look to ICE1712_AC97_* */
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#define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */
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#define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
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#define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */
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#define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */
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#define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */
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#define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */
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#define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */
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#define ICE1712_PLAYBACK_START 0x01 /* playback start */
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#define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
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#define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */
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#define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */
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#define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */
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#define ICE1712_CAPTURE_START 0x01 /* capture start */
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#define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */
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#define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */
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#define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */
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#define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */
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#define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */
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#define ICE1712_MT_MONITOR_RATE 0x3b /* byte */
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#define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */
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#define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */
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#define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */
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#define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */
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/*
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* Codec configuration bits
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*/
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/* PCI[60] System Configuration */
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#define ICE1712_CFG_CLOCK 0xc0
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#define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
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#define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
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#define ICE1712_CFG_EXT 0x80 /* external clock */
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#define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */
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#define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */
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#define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */
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#define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
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/* PCI[61] AC-Link Configuration */
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#define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
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#define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
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/* PCI[62] I2S Features */
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#define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
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#define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
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#define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
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#define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */
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/* PCI[63] S/PDIF Configuration */
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#define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */
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#define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
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#define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */
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/*
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* DMA mode values
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* identical with DMA_XXX on i386 architecture.
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*/
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#define ICE1712_DMA_MODE_WRITE 0x48
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#define ICE1712_DMA_AUTOINIT 0x10
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/*
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*
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*/
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struct snd_ice1712;
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struct snd_ice1712_eeprom {
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unsigned int subvendor; /* PCI[2c-2f] */
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unsigned char size; /* size of EEPROM image in bytes */
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unsigned char version; /* must be 1 (or 2 for vt1724) */
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unsigned char data[32];
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unsigned int gpiomask;
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unsigned int gpiostate;
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unsigned int gpiodir;
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};
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enum {
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ICE_EEP1_CODEC = 0, /* 06 */
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ICE_EEP1_ACLINK, /* 07 */
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ICE_EEP1_I2SID, /* 08 */
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ICE_EEP1_SPDIF, /* 09 */
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ICE_EEP1_GPIO_MASK, /* 0a */
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ICE_EEP1_GPIO_STATE, /* 0b */
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ICE_EEP1_GPIO_DIR, /* 0c */
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ICE_EEP1_AC97_MAIN_LO, /* 0d */
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ICE_EEP1_AC97_MAIN_HI, /* 0e */
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ICE_EEP1_AC97_PCM_LO, /* 0f */
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ICE_EEP1_AC97_PCM_HI, /* 10 */
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ICE_EEP1_AC97_REC_LO, /* 11 */
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ICE_EEP1_AC97_REC_HI, /* 12 */
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ICE_EEP1_AC97_RECSRC, /* 13 */
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ICE_EEP1_DAC_ID, /* 14 */
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ICE_EEP1_DAC_ID1,
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ICE_EEP1_DAC_ID2,
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ICE_EEP1_DAC_ID3,
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ICE_EEP1_ADC_ID, /* 18 */
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ICE_EEP1_ADC_ID1,
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ICE_EEP1_ADC_ID2,
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ICE_EEP1_ADC_ID3
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};
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#define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
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struct snd_ak4xxx_private {
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unsigned int cif: 1; /* CIF mode */
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unsigned char caddr; /* C0 and C1 bits */
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unsigned int data_mask; /* DATA gpio bit */
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unsigned int clk_mask; /* CLK gpio bit */
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unsigned int cs_mask; /* bit mask for select/deselect address */
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unsigned int cs_addr; /* bits to select address */
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unsigned int cs_none; /* bits to deselect address */
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unsigned int add_flags; /* additional bits at init */
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unsigned int mask_flags; /* total mask bits */
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struct snd_akm4xxx_ops {
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void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate);
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} ops;
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};
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struct snd_ice1712_spdif {
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unsigned char cs8403_bits;
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unsigned char cs8403_stream_bits;
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struct snd_kcontrol *stream_ctl;
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struct snd_ice1712_spdif_ops {
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void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *);
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void (*setup_rate)(struct snd_ice1712 *, int rate);
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void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *);
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void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
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int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
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void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
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int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
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} ops;
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};
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struct snd_ice1712 {
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unsigned long conp_dma_size;
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unsigned long conc_dma_size;
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unsigned long prop_dma_size;
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unsigned long proc_dma_size;
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int irq;
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unsigned long port;
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unsigned long ddma_port;
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unsigned long dmapath_port;
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unsigned long profi_port;
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struct pci_dev *pci;
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struct snd_card *card;
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struct snd_pcm *pcm;
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struct snd_pcm *pcm_ds;
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struct snd_pcm *pcm_pro;
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struct snd_pcm_substream *playback_con_substream;
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struct snd_pcm_substream *playback_con_substream_ds[6];
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struct snd_pcm_substream *capture_con_substream;
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struct snd_pcm_substream *playback_pro_substream;
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struct snd_pcm_substream *capture_pro_substream;
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unsigned int playback_pro_size;
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unsigned int capture_pro_size;
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unsigned int playback_con_virt_addr[6];
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unsigned int playback_con_active_buf[6];
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unsigned int capture_con_virt_addr;
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unsigned int ac97_ext_id;
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struct snd_ac97 *ac97;
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struct snd_rawmidi *rmidi[2];
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spinlock_t reg_lock;
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struct snd_info_entry *proc_entry;
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struct snd_ice1712_eeprom eeprom;
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unsigned int pro_volumes[20];
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unsigned int omni: 1; /* Delta Omni I/O */
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unsigned int dxr_enable: 1; /* Terratec DXR enable for DMX6FIRE */
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unsigned int vt1724: 1;
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unsigned int vt1720: 1;
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unsigned int has_spdif: 1; /* VT1720/4 - has SPDIF I/O */
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unsigned int force_pdma4: 1; /* VT1720/4 - PDMA4 as non-spdif */
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unsigned int force_rdma1: 1; /* VT1720/4 - RDMA1 as non-spdif */
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unsigned int num_total_dacs; /* total DACs */
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unsigned int num_total_adcs; /* total ADCs */
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unsigned int cur_rate; /* current rate */
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struct mutex open_mutex;
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struct snd_pcm_substream *pcm_reserved[4];
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struct snd_pcm_hw_constraint_list *hw_rates; /* card-specific rate constraints */
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unsigned int akm_codecs;
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struct snd_akm4xxx *akm;
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struct snd_ice1712_spdif spdif;
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struct mutex i2c_mutex; /* I2C mutex for ICE1724 registers */
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struct snd_i2c_bus *i2c; /* I2C bus */
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struct snd_i2c_device *cs8427; /* CS8427 I2C device */
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unsigned int cs8427_timeout; /* CS8427 reset timeout in HZ/100 */
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struct ice1712_gpio {
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unsigned int direction; /* current direction bits */
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unsigned int write_mask; /* current mask bits */
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unsigned int saved[2]; /* for ewx_i2c */
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/* operators */
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void (*set_mask)(struct snd_ice1712 *ice, unsigned int data);
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void (*set_dir)(struct snd_ice1712 *ice, unsigned int data);
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void (*set_data)(struct snd_ice1712 *ice, unsigned int data);
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unsigned int (*get_data)(struct snd_ice1712 *ice);
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/* misc operators - move to another place? */
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void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate);
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void (*i2s_mclk_changed)(struct snd_ice1712 *ice);
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} gpio;
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struct mutex gpio_mutex;
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/* other board-specific data */
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union {
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/* additional i2c devices for EWS boards */
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struct snd_i2c_device *i2cdevs[3];
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/* AC97 register cache for Aureon */
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struct aureon_spec {
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unsigned short stac9744[64];
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unsigned int cs8415_mux;
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unsigned short master[2];
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unsigned short vol[8];
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unsigned char pca9554_out;
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} aureon;
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/* AC97 register cache for Phase28 */
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struct phase28_spec {
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unsigned short master[2];
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unsigned short vol[8];
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} phase28;
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/* a non-standard I2C device for revo51 */
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struct revo51_spec {
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struct snd_i2c_device *dev;
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struct snd_pt2258 *pt2258;
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} revo51;
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/* Hoontech-specific setting */
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struct hoontech_spec {
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unsigned char boxbits[4];
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unsigned int config;
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unsigned short boxconfig[4];
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} hoontech;
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struct {
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struct ak4114 *ak4114;
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unsigned int analog: 1;
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} juli;
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struct {
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struct ak4114 *ak4114;
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} prodigy192;
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} spec;
|
|
|
|
};
|
|
|
|
|
|
/*
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|
* gpio access functions
|
|
*/
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|
static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits)
|
|
{
|
|
ice->gpio.set_dir(ice, bits);
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|
}
|
|
|
|
static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits)
|
|
{
|
|
ice->gpio.set_mask(ice, bits);
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|
}
|
|
|
|
static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val)
|
|
{
|
|
ice->gpio.set_data(ice, val);
|
|
}
|
|
|
|
static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice)
|
|
{
|
|
return ice->gpio.get_data(ice);
|
|
}
|
|
|
|
/*
|
|
* save and restore gpio status
|
|
* The access to gpio will be protected by mutex, so don't forget to
|
|
* restore!
|
|
*/
|
|
static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice)
|
|
{
|
|
mutex_lock(&ice->gpio_mutex);
|
|
ice->gpio.saved[0] = ice->gpio.direction;
|
|
ice->gpio.saved[1] = ice->gpio.write_mask;
|
|
}
|
|
|
|
static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice)
|
|
{
|
|
ice->gpio.set_dir(ice, ice->gpio.saved[0]);
|
|
ice->gpio.set_mask(ice, ice->gpio.saved[1]);
|
|
ice->gpio.direction = ice->gpio.saved[0];
|
|
ice->gpio.write_mask = ice->gpio.saved[1];
|
|
mutex_unlock(&ice->gpio_mutex);
|
|
}
|
|
|
|
/* for bit controls */
|
|
#define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
|
|
{ .iface = xiface, .name = xname, .access = xaccess, .info = snd_ice1712_gpio_info, \
|
|
.get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
|
|
.private_value = mask | (invert << 24) }
|
|
|
|
int snd_ice1712_gpio_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo);
|
|
int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
|
|
int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
|
|
|
|
/*
|
|
* set gpio direction, write mask and data
|
|
*/
|
|
static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice,
|
|
unsigned int mask, unsigned int bits)
|
|
{
|
|
ice->gpio.direction |= mask;
|
|
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
|
|
snd_ice1712_gpio_set_mask(ice, ~mask);
|
|
snd_ice1712_gpio_write(ice, mask & bits);
|
|
}
|
|
|
|
static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice,
|
|
unsigned int mask)
|
|
{
|
|
ice->gpio.direction &= ~mask;
|
|
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
|
|
return (snd_ice1712_gpio_read(ice) & mask);
|
|
}
|
|
|
|
int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice);
|
|
|
|
int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak, const struct snd_akm4xxx *template,
|
|
const struct snd_ak4xxx_private *priv, struct snd_ice1712 *ice);
|
|
void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice);
|
|
int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice);
|
|
|
|
int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr);
|
|
|
|
static inline void snd_ice1712_write(struct snd_ice1712 * ice, u8 addr, u8 data)
|
|
{
|
|
outb(addr, ICEREG(ice, INDEX));
|
|
outb(data, ICEREG(ice, DATA));
|
|
}
|
|
|
|
static inline u8 snd_ice1712_read(struct snd_ice1712 * ice, u8 addr)
|
|
{
|
|
outb(addr, ICEREG(ice, INDEX));
|
|
return inb(ICEREG(ice, DATA));
|
|
}
|
|
|
|
|
|
/*
|
|
* entry pointer
|
|
*/
|
|
|
|
struct snd_ice1712_card_info {
|
|
unsigned int subvendor;
|
|
char *name;
|
|
char *model;
|
|
char *driver;
|
|
int (*chip_init)(struct snd_ice1712 *);
|
|
int (*build_controls)(struct snd_ice1712 *);
|
|
unsigned int no_mpu401: 1;
|
|
unsigned int mpu401_1_info_flags;
|
|
unsigned int mpu401_2_info_flags;
|
|
const char *mpu401_1_name;
|
|
const char *mpu401_2_name;
|
|
const unsigned int eeprom_size;
|
|
const unsigned char *eeprom_data;
|
|
};
|
|
|
|
|
|
#endif /* __SOUND_ICE1712_H */
|