622 lines
16 KiB
C
622 lines
16 KiB
C
/*
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* linux/arch/alpha/kernel/core_t2.c
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*
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* Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
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* December 1996.
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*
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* based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
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*
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* Code common to all T2 core logic chips.
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*/
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#define __EXTERN_INLINE
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#include <asm/io.h>
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#include <asm/core_t2.h>
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#undef __EXTERN_INLINE
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/delay.h>
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#include "proto.h"
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#include "pci_impl.h"
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/* For dumping initial DMA window settings. */
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#define DEBUG_PRINT_INITIAL_SETTINGS 0
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/* For dumping final DMA window settings. */
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#define DEBUG_PRINT_FINAL_SETTINGS 0
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/*
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* By default, we direct-map starting at 2GB, in order to allow the
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* maximum size direct-map window (2GB) to match the maximum amount of
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* memory (2GB) that can be present on SABLEs. But that limits the
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* floppy to DMA only via the scatter/gather window set up for 8MB
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* ISA DMA, since the maximum ISA DMA address is 2GB-1.
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*
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* For now, this seems a reasonable trade-off: even though most SABLEs
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* have less than 1GB of memory, floppy usage/performance will not
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* really be affected by forcing it to go via scatter/gather...
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*/
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#define T2_DIRECTMAP_2G 1
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#if T2_DIRECTMAP_2G
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# define T2_DIRECTMAP_START 0x80000000UL
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# define T2_DIRECTMAP_LENGTH 0x80000000UL
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#else
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# define T2_DIRECTMAP_START 0x40000000UL
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# define T2_DIRECTMAP_LENGTH 0x40000000UL
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#endif
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/* The ISA scatter/gather window settings. */
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#define T2_ISA_SG_START 0x00800000UL
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#define T2_ISA_SG_LENGTH 0x00800000UL
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/*
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* NOTE: Herein lie back-to-back mb instructions. They are magic.
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* One plausible explanation is that the i/o controller does not properly
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* handle the system transaction. Another involves timing. Ho hum.
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*/
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/*
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* BIOS32-style PCI interface:
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*/
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#define DEBUG_CONFIG 0
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#if DEBUG_CONFIG
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# define DBG(args) printk args
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#else
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# define DBG(args)
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#endif
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static volatile unsigned int t2_mcheck_any_expected;
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static volatile unsigned int t2_mcheck_last_taken;
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/* Place to save the DMA Window registers as set up by SRM
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for restoration during shutdown. */
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static struct
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{
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struct {
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unsigned long wbase;
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unsigned long wmask;
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unsigned long tbase;
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} window[2];
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unsigned long hae_1;
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unsigned long hae_2;
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unsigned long hae_3;
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unsigned long hae_4;
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unsigned long hbase;
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} t2_saved_config __attribute((common));
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/*
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* Given a bus, device, and function number, compute resulting
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* configuration space address and setup the T2_HAXR2 register
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* accordingly. It is therefore not safe to have concurrent
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* invocations to configuration space access routines, but there
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* really shouldn't be any need for this.
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*
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* Type 0:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:11 Device select bit.
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* 10:8 Function number
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* 7:2 Register number
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*
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* Type 1:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:24 reserved
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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* Notes:
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* The function number selects which function of a multi-function device
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* (e.g., SCSI and Ethernet).
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*
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* The register selects a DWORD (32 bit) register offset. Hence it
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two
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* bits.
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*/
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static int
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr, unsigned char *type1)
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{
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unsigned long addr;
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u8 bus = pbus->number;
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DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
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" addr=0x%lx, type1=0x%x)\n",
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bus, device_fn, where, pci_addr, type1));
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if (bus == 0) {
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int device = device_fn >> 3;
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/* Type 0 configuration cycle. */
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if (device > 8) {
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DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
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device));
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return -1;
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}
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*type1 = 0;
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addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where);
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} else {
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/* Type 1 configuration cycle. */
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*type1 = 1;
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addr = (bus << 16) | (device_fn << 8) | (where);
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}
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*pci_addr = addr;
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DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
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return 0;
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}
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/*
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* NOTE: both conf_read() and conf_write() may set HAE_3 when needing
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* to do type1 access. This is protected by the use of spinlock IRQ
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* primitives in the wrapper functions pci_{read,write}_config_*()
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* defined in drivers/pci/pci.c.
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*/
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static unsigned int
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conf_read(unsigned long addr, unsigned char type1)
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{
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unsigned int value, cpu, taken;
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unsigned long t2_cfg = 0;
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cpu = smp_processor_id();
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DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
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/* If Type1 access, must set T2 CFG. */
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if (type1) {
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t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
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*(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
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mb();
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}
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mb();
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draina();
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mcheck_expected(cpu) = 1;
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mcheck_taken(cpu) = 0;
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t2_mcheck_any_expected |= (1 << cpu);
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mb();
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/* Access configuration space. */
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value = *(vuip)addr;
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mb();
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mb(); /* magic */
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/* Wait for possible mcheck. Also, this lets other CPUs clear
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their mchecks as well, as they can reliably tell when
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another CPU is in the midst of handling a real mcheck via
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the "taken" function. */
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udelay(100);
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if ((taken = mcheck_taken(cpu))) {
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mcheck_taken(cpu) = 0;
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t2_mcheck_last_taken |= (1 << cpu);
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value = 0xffffffffU;
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mb();
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}
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mcheck_expected(cpu) = 0;
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t2_mcheck_any_expected = 0;
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mb();
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/* If Type1 access, must reset T2 CFG so normal IO space ops work. */
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if (type1) {
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*(vulp)T2_HAE_3 = t2_cfg;
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mb();
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}
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return value;
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}
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static void
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conf_write(unsigned long addr, unsigned int value, unsigned char type1)
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{
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unsigned int cpu, taken;
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unsigned long t2_cfg = 0;
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cpu = smp_processor_id();
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/* If Type1 access, must set T2 CFG. */
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if (type1) {
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t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
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*(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
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mb();
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}
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mb();
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draina();
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mcheck_expected(cpu) = 1;
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mcheck_taken(cpu) = 0;
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t2_mcheck_any_expected |= (1 << cpu);
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mb();
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/* Access configuration space. */
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*(vuip)addr = value;
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mb();
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mb(); /* magic */
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/* Wait for possible mcheck. Also, this lets other CPUs clear
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their mchecks as well, as they can reliably tell when
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this CPU is in the midst of handling a real mcheck via
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the "taken" function. */
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udelay(100);
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if ((taken = mcheck_taken(cpu))) {
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mcheck_taken(cpu) = 0;
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t2_mcheck_last_taken |= (1 << cpu);
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mb();
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}
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mcheck_expected(cpu) = 0;
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t2_mcheck_any_expected = 0;
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mb();
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/* If Type1 access, must reset T2 CFG so normal IO space ops work. */
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if (type1) {
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*(vulp)T2_HAE_3 = t2_cfg;
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mb();
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}
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}
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static int
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t2_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr, pci_addr;
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unsigned char type1;
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int shift;
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long mask;
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if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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mask = (size - 1) * 8;
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shift = (where & 3) * 8;
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addr = (pci_addr << 5) + mask + T2_CONF;
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*value = conf_read(addr, type1) >> (shift);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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t2_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
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u32 value)
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{
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unsigned long addr, pci_addr;
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unsigned char type1;
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long mask;
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if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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mask = (size - 1) * 8;
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addr = (pci_addr << 5) + mask + T2_CONF;
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conf_write(addr, value << ((where & 3) * 8), type1);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops t2_pci_ops =
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{
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.read = t2_read_config,
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.write = t2_write_config,
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};
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static void __init
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t2_direct_map_window1(unsigned long base, unsigned long length)
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{
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unsigned long temp;
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__direct_map_base = base;
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__direct_map_size = length;
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temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
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*(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
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temp = (length - 1) & 0xfff00000UL;
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*(vulp)T2_WMASK1 = temp;
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*(vulp)T2_TBASE1 = 0;
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#if DEBUG_PRINT_FINAL_SETTINGS
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printk("%s: setting WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",
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__FUNCTION__,
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*(vulp)T2_WBASE1,
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*(vulp)T2_WMASK1,
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*(vulp)T2_TBASE1);
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#endif
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}
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static void __init
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t2_sg_map_window2(struct pci_controller *hose,
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unsigned long base,
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unsigned long length)
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{
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unsigned long temp;
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/* Note we can only do 1 SG window, as the other is for direct, so
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do an ISA SG area, especially for the floppy. */
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hose->sg_isa = iommu_arena_new(hose, base, length, 0);
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hose->sg_pci = NULL;
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temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
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*(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */
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temp = (length - 1) & 0xfff00000UL;
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*(vulp)T2_WMASK2 = temp;
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*(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;
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mb();
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t2_pci_tbi(hose, 0, -1); /* flush TLB all */
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#if DEBUG_PRINT_FINAL_SETTINGS
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printk("%s: setting WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",
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__FUNCTION__,
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*(vulp)T2_WBASE2,
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*(vulp)T2_WMASK2,
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*(vulp)T2_TBASE2);
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#endif
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}
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static void __init
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t2_save_configuration(void)
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{
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#if DEBUG_PRINT_INITIAL_SETTINGS
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printk("%s: HAE_1 was 0x%lx\n", __FUNCTION__, srm_hae); /* HW is 0 */
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printk("%s: HAE_2 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_2);
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printk("%s: HAE_3 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_3);
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printk("%s: HAE_4 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_4);
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printk("%s: HBASE was 0x%lx\n", __FUNCTION__, *(vulp)T2_HBASE);
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printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __FUNCTION__,
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*(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
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printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __FUNCTION__,
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*(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
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#endif
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/*
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* Save the DMA Window registers.
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*/
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t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;
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t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;
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t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;
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t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;
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t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;
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t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;
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t2_saved_config.hae_1 = srm_hae; /* HW is already set to 0 */
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t2_saved_config.hae_2 = *(vulp)T2_HAE_2;
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t2_saved_config.hae_3 = *(vulp)T2_HAE_3;
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t2_saved_config.hae_4 = *(vulp)T2_HAE_4;
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t2_saved_config.hbase = *(vulp)T2_HBASE;
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}
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void __init
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t2_init_arch(void)
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{
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struct pci_controller *hose;
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unsigned long temp;
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unsigned int i;
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for (i = 0; i < NR_CPUS; i++) {
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mcheck_expected(i) = 0;
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mcheck_taken(i) = 0;
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}
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t2_mcheck_any_expected = 0;
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t2_mcheck_last_taken = 0;
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/* Enable scatter/gather TLB use. */
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temp = *(vulp)T2_IOCSR;
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if (!(temp & (0x1UL << 26))) {
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printk("t2_init_arch: enabling SG TLB, IOCSR was 0x%lx\n",
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temp);
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*(vulp)T2_IOCSR = temp | (0x1UL << 26);
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mb();
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*(vulp)T2_IOCSR; /* read it back to make sure */
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}
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t2_save_configuration();
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/*
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* Create our single hose.
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*/
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pci_isa_hose = hose = alloc_pci_controller();
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hose->io_space = &ioport_resource;
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hose->mem_space = &iomem_resource;
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hose->index = 0;
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hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR;
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hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR;
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hose->sparse_io_base = T2_IO - IDENT_ADDR;
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hose->dense_io_base = 0;
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/*
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* Set up the PCI->physical memory translation windows.
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*
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* Window 1 is direct mapped.
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* Window 2 is scatter/gather (for ISA).
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*/
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t2_direct_map_window1(T2_DIRECTMAP_START, T2_DIRECTMAP_LENGTH);
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/* Always make an ISA DMA window. */
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t2_sg_map_window2(hose, T2_ISA_SG_START, T2_ISA_SG_LENGTH);
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*(vulp)T2_HBASE = 0x0; /* Disable HOLES. */
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/* Zero HAE. */
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*(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */
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*(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */
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*(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */
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/*
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* We also now zero out HAE_4, the dense memory HAE, so that
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* we need not account for its "offset" when accessing dense
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* memory resources which we allocated in our normal way. This
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* HAE would need to stay untouched were we to keep the SRM
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* resource settings.
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*
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* Thus we can now run standard X servers on SABLE/LYNX. :-)
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*/
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*(vulp)T2_HAE_4 = 0; mb();
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}
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void
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t2_kill_arch(int mode)
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{
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/*
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* Restore the DMA Window registers.
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*/
|
||
*(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;
|
||
*(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;
|
||
*(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;
|
||
*(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;
|
||
*(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;
|
||
*(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;
|
||
mb();
|
||
|
||
*(vulp)T2_HAE_1 = srm_hae;
|
||
*(vulp)T2_HAE_2 = t2_saved_config.hae_2;
|
||
*(vulp)T2_HAE_3 = t2_saved_config.hae_3;
|
||
*(vulp)T2_HAE_4 = t2_saved_config.hae_4;
|
||
*(vulp)T2_HBASE = t2_saved_config.hbase;
|
||
mb();
|
||
*(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */
|
||
}
|
||
|
||
void
|
||
t2_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
|
||
{
|
||
unsigned long t2_iocsr;
|
||
|
||
t2_iocsr = *(vulp)T2_IOCSR;
|
||
|
||
/* set the TLB Clear bit */
|
||
*(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);
|
||
mb();
|
||
*(vulp)T2_IOCSR; /* read it back to make sure */
|
||
|
||
/* clear the TLB Clear bit */
|
||
*(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);
|
||
mb();
|
||
*(vulp)T2_IOCSR; /* read it back to make sure */
|
||
}
|
||
|
||
#define SIC_SEIC (1UL << 33) /* System Event Clear */
|
||
|
||
static void
|
||
t2_clear_errors(int cpu)
|
||
{
|
||
struct sable_cpu_csr *cpu_regs;
|
||
|
||
cpu_regs = (struct sable_cpu_csr *)T2_CPUn_BASE(cpu);
|
||
|
||
cpu_regs->sic &= ~SIC_SEIC;
|
||
|
||
/* Clear CPU errors. */
|
||
cpu_regs->bcce |= cpu_regs->bcce;
|
||
cpu_regs->cbe |= cpu_regs->cbe;
|
||
cpu_regs->bcue |= cpu_regs->bcue;
|
||
cpu_regs->dter |= cpu_regs->dter;
|
||
|
||
*(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
|
||
*(vulp)T2_PERR1 |= *(vulp)T2_PERR1;
|
||
|
||
mb();
|
||
mb(); /* magic */
|
||
}
|
||
|
||
/*
|
||
* SABLE seems to have a "broadcast" style machine check, in that all
|
||
* CPUs receive it. And, the issuing CPU, in the case of PCI Config
|
||
* space read/write faults, will also receive a second mcheck, upon
|
||
* lowering IPL during completion processing in pci_read_config_byte()
|
||
* et al.
|
||
*
|
||
* Hence all the taken/expected/any_expected/last_taken stuff...
|
||
*/
|
||
void
|
||
t2_machine_check(unsigned long vector, unsigned long la_ptr)
|
||
{
|
||
int cpu = smp_processor_id();
|
||
#ifdef CONFIG_VERBOSE_MCHECK
|
||
struct el_common *mchk_header = (struct el_common *)la_ptr;
|
||
#endif
|
||
|
||
/* Clear the error before any reporting. */
|
||
mb();
|
||
mb(); /* magic */
|
||
draina();
|
||
t2_clear_errors(cpu);
|
||
|
||
/* This should not actually be done until the logout frame is
|
||
examined, but, since we don't do that, go on and do this... */
|
||
wrmces(0x7);
|
||
mb();
|
||
|
||
/* Now, do testing for the anomalous conditions. */
|
||
if (!mcheck_expected(cpu) && t2_mcheck_any_expected) {
|
||
/*
|
||
* FUNKY: Received mcheck on a CPU and not
|
||
* expecting it, but another CPU is expecting one.
|
||
*
|
||
* Just dismiss it for now on this CPU...
|
||
*/
|
||
#ifdef CONFIG_VERBOSE_MCHECK
|
||
if (alpha_verbose_mcheck > 1) {
|
||
printk("t2_machine_check(cpu%d): any_expected 0x%x -"
|
||
" (assumed) spurious -"
|
||
" code 0x%x\n", cpu, t2_mcheck_any_expected,
|
||
(unsigned int)mchk_header->code);
|
||
}
|
||
#endif
|
||
return;
|
||
}
|
||
|
||
if (!mcheck_expected(cpu) && !t2_mcheck_any_expected) {
|
||
if (t2_mcheck_last_taken & (1 << cpu)) {
|
||
#ifdef CONFIG_VERBOSE_MCHECK
|
||
if (alpha_verbose_mcheck > 1) {
|
||
printk("t2_machine_check(cpu%d): last_taken 0x%x - "
|
||
"unexpected mcheck - code 0x%x\n",
|
||
cpu, t2_mcheck_last_taken,
|
||
(unsigned int)mchk_header->code);
|
||
}
|
||
#endif
|
||
t2_mcheck_last_taken = 0;
|
||
mb();
|
||
return;
|
||
} else {
|
||
t2_mcheck_last_taken = 0;
|
||
mb();
|
||
}
|
||
}
|
||
|
||
#ifdef CONFIG_VERBOSE_MCHECK
|
||
if (alpha_verbose_mcheck > 1) {
|
||
printk("%s t2_mcheck(cpu%d): last_taken 0x%x - "
|
||
"any_expected 0x%x - code 0x%x\n",
|
||
(mcheck_expected(cpu) ? "EX" : "UN"), cpu,
|
||
t2_mcheck_last_taken, t2_mcheck_any_expected,
|
||
(unsigned int)mchk_header->code);
|
||
}
|
||
#endif
|
||
|
||
process_mcheck_info(vector, la_ptr, "T2", mcheck_expected(cpu));
|
||
}
|