444 lines
12 KiB
C
444 lines
12 KiB
C
/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for s3c24xx external clock output.
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*/
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#include <linux/clkdev.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include "clk.h"
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/* legacy access to misccr, until dt conversion is finished */
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#include <mach/hardware.h>
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#include <mach/regs-gpio.h>
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#define MUX_DCLK0 0
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#define MUX_DCLK1 1
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#define DIV_DCLK0 2
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#define DIV_DCLK1 3
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#define GATE_DCLK0 4
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#define GATE_DCLK1 5
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#define MUX_CLKOUT0 6
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#define MUX_CLKOUT1 7
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#define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
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enum supported_socs {
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S3C2410,
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S3C2412,
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S3C2440,
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S3C2443,
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};
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struct s3c24xx_dclk_drv_data {
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const char **clkout0_parent_names;
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int clkout0_num_parents;
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const char **clkout1_parent_names;
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int clkout1_num_parents;
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const char **mux_parent_names;
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int mux_num_parents;
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};
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/*
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* Clock for output-parent selection in misccr
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*/
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struct s3c24xx_clkout {
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struct clk_hw hw;
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u32 mask;
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u8 shift;
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};
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#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
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static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
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{
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struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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u32 val;
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val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
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val >>= clkout->shift;
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val &= clkout->mask;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
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{
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struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
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s3c2410_modify_misccr((clkout->mask << clkout->shift),
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(index << clkout->shift));
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return 0;
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}
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static const struct clk_ops s3c24xx_clkout_ops = {
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.get_parent = s3c24xx_clkout_get_parent,
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.set_parent = s3c24xx_clkout_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents,
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u8 shift, u32 mask)
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{
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struct s3c24xx_clkout *clkout;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the clkout */
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clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
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if (!clkout)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &s3c24xx_clkout_ops;
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init.flags = CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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clkout->shift = shift;
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clkout->mask = mask;
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clkout->hw.init = &init;
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clk = clk_register(dev, &clkout->hw);
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return clk;
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}
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/*
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* dclk and clkout init
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*/
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struct s3c24xx_dclk {
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struct device *dev;
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void __iomem *base;
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struct clk_onecell_data clk_data;
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struct notifier_block dclk0_div_change_nb;
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struct notifier_block dclk1_div_change_nb;
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spinlock_t dclk_lock;
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unsigned long reg_save;
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};
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#define to_s3c24xx_dclk0(x) \
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container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
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#define to_s3c24xx_dclk1(x) \
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container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
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static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
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static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
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"gate_dclk0" };
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static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
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"gate_dclk1" };
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static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
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"hclk", "pclk", "gate_dclk0" };
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static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
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"gate_dclk1" };
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static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
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"gate_dclk0" };
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static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
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"hclk", "pclk", "gate_dclk1" };
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static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
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static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
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"gate_dclk0" };
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static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
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"hclk", "pclk", "gate_dclk1" };
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#define DCLKCON_DCLK_DIV_MASK 0xf
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#define DCLKCON_DCLK0_DIV_SHIFT 4
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#define DCLKCON_DCLK0_CMP_SHIFT 8
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#define DCLKCON_DCLK1_DIV_SHIFT 20
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#define DCLKCON_DCLK1_CMP_SHIFT 24
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static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
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int div_shift, int cmp_shift)
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{
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unsigned long flags = 0;
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u32 dclk_con, div, cmp;
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spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
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dclk_con = readl_relaxed(s3c24xx_dclk->base);
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div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
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cmp = ((div + 1) / 2) - 1;
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dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
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dclk_con |= (cmp << cmp_shift);
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writel_relaxed(dclk_con, s3c24xx_dclk->base);
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spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
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}
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static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
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if (event == POST_RATE_CHANGE) {
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s3c24xx_dclk_update_cmp(s3c24xx_dclk,
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DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
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}
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return NOTIFY_DONE;
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}
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static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
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if (event == POST_RATE_CHANGE) {
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s3c24xx_dclk_update_cmp(s3c24xx_dclk,
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DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
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}
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return NOTIFY_DONE;
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}
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#ifdef CONFIG_PM_SLEEP
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static int s3c24xx_dclk_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
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s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
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return 0;
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}
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static int s3c24xx_dclk_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
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writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
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s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
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static int s3c24xx_dclk_probe(struct platform_device *pdev)
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{
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struct s3c24xx_dclk *s3c24xx_dclk;
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struct resource *mem;
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struct clk **clk_table;
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struct s3c24xx_dclk_drv_data *dclk_variant;
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int ret, i;
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s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk),
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GFP_KERNEL);
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if (!s3c24xx_dclk)
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return -ENOMEM;
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s3c24xx_dclk->dev = &pdev->dev;
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platform_set_drvdata(pdev, s3c24xx_dclk);
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spin_lock_init(&s3c24xx_dclk->dclk_lock);
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clk_table = devm_kzalloc(&pdev->dev,
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sizeof(struct clk *) * DCLK_MAX_CLKS,
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GFP_KERNEL);
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if (!clk_table)
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return -ENOMEM;
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s3c24xx_dclk->clk_data.clks = clk_table;
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s3c24xx_dclk->clk_data.clk_num = DCLK_MAX_CLKS;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(s3c24xx_dclk->base))
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return PTR_ERR(s3c24xx_dclk->base);
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dclk_variant = (struct s3c24xx_dclk_drv_data *)
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platform_get_device_id(pdev)->driver_data;
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clk_table[MUX_DCLK0] = clk_register_mux(&pdev->dev, "mux_dclk0",
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dclk_variant->mux_parent_names,
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dclk_variant->mux_num_parents, 0,
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s3c24xx_dclk->base, 1, 1, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[MUX_DCLK1] = clk_register_mux(&pdev->dev, "mux_dclk1",
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dclk_variant->mux_parent_names,
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dclk_variant->mux_num_parents, 0,
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s3c24xx_dclk->base, 17, 1, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[DIV_DCLK0] = clk_register_divider(&pdev->dev, "div_dclk0",
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"mux_dclk0", 0, s3c24xx_dclk->base,
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4, 4, 0, &s3c24xx_dclk->dclk_lock);
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clk_table[DIV_DCLK1] = clk_register_divider(&pdev->dev, "div_dclk1",
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"mux_dclk1", 0, s3c24xx_dclk->base,
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20, 4, 0, &s3c24xx_dclk->dclk_lock);
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clk_table[GATE_DCLK0] = clk_register_gate(&pdev->dev, "gate_dclk0",
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"div_dclk0", CLK_SET_RATE_PARENT,
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s3c24xx_dclk->base, 0, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[GATE_DCLK1] = clk_register_gate(&pdev->dev, "gate_dclk1",
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"div_dclk1", CLK_SET_RATE_PARENT,
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s3c24xx_dclk->base, 16, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
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"clkout0", dclk_variant->clkout0_parent_names,
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dclk_variant->clkout0_num_parents, 4, 7);
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clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
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"clkout1", dclk_variant->clkout1_parent_names,
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dclk_variant->clkout1_num_parents, 8, 7);
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for (i = 0; i < DCLK_MAX_CLKS; i++)
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if (IS_ERR(clk_table[i])) {
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dev_err(&pdev->dev, "clock %d failed to register\n", i);
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ret = PTR_ERR(clk_table[i]);
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goto err_clk_register;
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}
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ret = clk_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
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if (!ret)
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ret = clk_register_clkdev(clk_table[MUX_DCLK1], "dclk1", NULL);
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if (!ret)
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ret = clk_register_clkdev(clk_table[MUX_CLKOUT0],
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"clkout0", NULL);
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if (!ret)
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ret = clk_register_clkdev(clk_table[MUX_CLKOUT1],
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"clkout1", NULL);
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if (ret) {
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dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
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goto err_clk_register;
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}
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s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
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s3c24xx_dclk0_div_notify;
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s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
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s3c24xx_dclk1_div_notify;
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ret = clk_notifier_register(clk_table[DIV_DCLK0],
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&s3c24xx_dclk->dclk0_div_change_nb);
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if (ret)
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goto err_clk_register;
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ret = clk_notifier_register(clk_table[DIV_DCLK1],
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&s3c24xx_dclk->dclk1_div_change_nb);
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if (ret)
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goto err_dclk_notify;
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return 0;
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err_dclk_notify:
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clk_notifier_unregister(clk_table[DIV_DCLK0],
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&s3c24xx_dclk->dclk0_div_change_nb);
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err_clk_register:
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for (i = 0; i < DCLK_MAX_CLKS; i++)
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if (clk_table[i] && !IS_ERR(clk_table[i]))
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clk_unregister(clk_table[i]);
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return ret;
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}
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static int s3c24xx_dclk_remove(struct platform_device *pdev)
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{
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struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
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struct clk **clk_table = s3c24xx_dclk->clk_data.clks;
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int i;
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clk_notifier_unregister(clk_table[DIV_DCLK1],
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&s3c24xx_dclk->dclk1_div_change_nb);
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clk_notifier_unregister(clk_table[DIV_DCLK0],
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&s3c24xx_dclk->dclk0_div_change_nb);
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for (i = 0; i < DCLK_MAX_CLKS; i++)
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clk_unregister(clk_table[i]);
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return 0;
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}
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static struct s3c24xx_dclk_drv_data dclk_variants[] = {
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[S3C2410] = {
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.clkout0_parent_names = clkout0_s3c2410_p,
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.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
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.clkout1_parent_names = clkout1_s3c2410_p,
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.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
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.mux_parent_names = dclk_s3c2410_p,
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.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
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},
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[S3C2412] = {
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.clkout0_parent_names = clkout0_s3c2412_p,
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.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
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.clkout1_parent_names = clkout1_s3c2412_p,
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.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
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.mux_parent_names = dclk_s3c2410_p,
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.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
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},
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[S3C2440] = {
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.clkout0_parent_names = clkout0_s3c2440_p,
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.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
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.clkout1_parent_names = clkout1_s3c2440_p,
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.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
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.mux_parent_names = dclk_s3c2410_p,
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.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
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},
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[S3C2443] = {
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.clkout0_parent_names = clkout0_s3c2443_p,
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.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
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.clkout1_parent_names = clkout1_s3c2443_p,
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.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
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.mux_parent_names = dclk_s3c2443_p,
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.mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
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},
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};
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static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
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{
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.name = "s3c2410-dclk",
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.driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
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}, {
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.name = "s3c2412-dclk",
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.driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
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}, {
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.name = "s3c2440-dclk",
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.driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
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}, {
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.name = "s3c2443-dclk",
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.driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
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},
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{ }
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};
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MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
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static struct platform_driver s3c24xx_dclk_driver = {
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.driver = {
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.name = "s3c24xx-dclk",
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.pm = &s3c24xx_dclk_pm_ops,
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.suppress_bind_attrs = true,
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},
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.probe = s3c24xx_dclk_probe,
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.remove = s3c24xx_dclk_remove,
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.id_table = s3c24xx_dclk_driver_ids,
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|
};
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module_platform_driver(s3c24xx_dclk_driver);
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|
|
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
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MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");
|