261 lines
6.8 KiB
C
261 lines
6.8 KiB
C
/*
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* linux/drivers/usb/gadget/lh7a40x_udc.h
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* Sharp LH7A40x on-chip full speed USB device controllers
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*
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* Copyright (C) 2004 Mikko Lahteenmaki, Nordic ID
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* Copyright (C) 2004 Bo Henriksen, Nordic ID
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __LH7A40X_H_
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#define __LH7A40X_H_
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/timer.h>
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#include <linux/proc_fs.h>
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#include <linux/mm.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <asm/byteorder.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/unaligned.h>
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#include <asm/hardware.h>
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#include <linux/usb_ch9.h>
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#include <linux/usb_gadget.h>
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/*
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* Memory map
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*/
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#define USB_FA 0x80000200 // function address register
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#define USB_PM 0x80000204 // power management register
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#define USB_IN_INT 0x80000208 // IN interrupt register bank (EP0-EP3)
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#define USB_OUT_INT 0x80000210 // OUT interrupt register bank (EP2)
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#define USB_INT 0x80000218 // interrupt register bank
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#define USB_IN_INT_EN 0x8000021C // IN interrupt enable register bank
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#define USB_OUT_INT_EN 0x80000224 // OUT interrupt enable register bank
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#define USB_INT_EN 0x8000022C // USB interrupt enable register bank
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#define USB_FRM_NUM1 0x80000230 // Frame number1 register
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#define USB_FRM_NUM2 0x80000234 // Frame number2 register
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#define USB_INDEX 0x80000238 // index register
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#define USB_IN_MAXP 0x80000240 // IN MAXP register
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#define USB_IN_CSR1 0x80000244 // IN CSR1 register/EP0 CSR register
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#define USB_EP0_CSR 0x80000244 // IN CSR1 register/EP0 CSR register
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#define USB_IN_CSR2 0x80000248 // IN CSR2 register
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#define USB_OUT_MAXP 0x8000024C // OUT MAXP register
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#define USB_OUT_CSR1 0x80000250 // OUT CSR1 register
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#define USB_OUT_CSR2 0x80000254 // OUT CSR2 register
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#define USB_OUT_FIFO_WC1 0x80000258 // OUT FIFO write count1 register
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#define USB_OUT_FIFO_WC2 0x8000025C // OUT FIFO write count2 register
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#define USB_RESET 0x8000044C // USB reset register
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#define USB_EP0_FIFO 0x80000280
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#define USB_EP1_FIFO 0x80000284
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#define USB_EP2_FIFO 0x80000288
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#define USB_EP3_FIFO 0x8000028c
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/*
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* USB reset register
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*/
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#define USB_RESET_APB (1<<1) //resets USB APB control side WRITE
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#define USB_RESET_IO (1<<0) //resets USB IO side WRITE
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/*
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* USB function address register
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*/
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#define USB_FA_ADDR_UPDATE (1<<7)
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#define USB_FA_FUNCTION_ADDR (0x7F)
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/*
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* Power Management register
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*/
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#define PM_USB_DCP (1<<5)
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#define PM_USB_ENABLE (1<<4)
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#define PM_USB_RESET (1<<3)
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#define PM_UC_RESUME (1<<2)
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#define PM_SUSPEND_MODE (1<<1)
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#define PM_ENABLE_SUSPEND (1<<0)
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/*
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* IN interrupt register
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*/
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#define USB_IN_INT_EP3 (1<<3)
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#define USB_IN_INT_EP1 (1<<1)
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#define USB_IN_INT_EP0 (1<<0)
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/*
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* OUT interrupt register
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*/
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#define USB_OUT_INT_EP2 (1<<2)
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/*
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* USB interrupt register
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*/
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#define USB_INT_RESET_INT (1<<2)
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#define USB_INT_RESUME_INT (1<<1)
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#define USB_INT_SUSPEND_INT (1<<0)
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/*
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* USB interrupt enable register
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*/
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#define USB_INT_EN_USB_RESET_INTER (1<<2)
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#define USB_INT_EN_RESUME_INTER (1<<1)
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#define USB_INT_EN_SUSPEND_INTER (1<<0)
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/*
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* INCSR1 register
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*/
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#define USB_IN_CSR1_CLR_DATA_TOGGLE (1<<6)
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#define USB_IN_CSR1_SENT_STALL (1<<5)
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#define USB_IN_CSR1_SEND_STALL (1<<4)
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#define USB_IN_CSR1_FIFO_FLUSH (1<<3)
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#define USB_IN_CSR1_FIFO_NOT_EMPTY (1<<1)
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#define USB_IN_CSR1_IN_PKT_RDY (1<<0)
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/*
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* INCSR2 register
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*/
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#define USB_IN_CSR2_AUTO_SET (1<<7)
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#define USB_IN_CSR2_USB_DMA_EN (1<<4)
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/*
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* OUT CSR1 register
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*/
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#define USB_OUT_CSR1_CLR_DATA_REG (1<<7)
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#define USB_OUT_CSR1_SENT_STALL (1<<6)
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#define USB_OUT_CSR1_SEND_STALL (1<<5)
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#define USB_OUT_CSR1_FIFO_FLUSH (1<<4)
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#define USB_OUT_CSR1_FIFO_FULL (1<<1)
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#define USB_OUT_CSR1_OUT_PKT_RDY (1<<0)
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/*
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* OUT CSR2 register
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*/
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#define USB_OUT_CSR2_AUTO_CLR (1<<7)
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#define USB_OUT_CSR2_USB_DMA_EN (1<<4)
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/*
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* EP0 CSR
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*/
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#define EP0_CLR_SETUP_END (1<<7) /* Clear "Setup Ends" Bit (w) */
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#define EP0_CLR_OUT (1<<6) /* Clear "Out packet ready" Bit (w) */
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#define EP0_SEND_STALL (1<<5) /* Send STALL Handshake (rw) */
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#define EP0_SETUP_END (1<<4) /* Setup Ends (r) */
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#define EP0_DATA_END (1<<3) /* Data end (rw) */
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#define EP0_SENT_STALL (1<<2) /* Sent Stall Handshake (r) */
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#define EP0_IN_PKT_RDY (1<<1) /* In packet ready (rw) */
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#define EP0_OUT_PKT_RDY (1<<0) /* Out packet ready (r) */
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/* general CSR */
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#define OUT_PKT_RDY (1<<0)
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#define IN_PKT_RDY (1<<0)
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/*
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* IN/OUT MAXP register
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*/
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#define USB_OUT_MAXP_MAXP (0xF)
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#define USB_IN_MAXP_MAXP (0xF)
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// Max packet size
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//#define EP0_PACKETSIZE 0x10
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#define EP0_PACKETSIZE 0x8
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#define EP0_MAXPACKETSIZE 0x10
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#define UDC_MAX_ENDPOINTS 4
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#define WAIT_FOR_SETUP 0
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#define DATA_STATE_XMIT 1
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#define DATA_STATE_NEED_ZLP 2
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#define WAIT_FOR_OUT_STATUS 3
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#define DATA_STATE_RECV 4
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/* ********************************************************************************************* */
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/* IO
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*/
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typedef enum ep_type {
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ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
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} ep_type_t;
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struct lh7a40x_ep {
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struct usb_ep ep;
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struct lh7a40x_udc *dev;
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const struct usb_endpoint_descriptor *desc;
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struct list_head queue;
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unsigned long pio_irqs;
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u8 stopped;
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u8 bEndpointAddress;
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u8 bmAttributes;
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ep_type_t ep_type;
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u32 fifo;
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u32 csr1;
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u32 csr2;
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};
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struct lh7a40x_request {
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struct usb_request req;
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struct list_head queue;
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};
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struct lh7a40x_udc {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct device *dev;
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spinlock_t lock;
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int ep0state;
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struct lh7a40x_ep ep[UDC_MAX_ENDPOINTS];
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unsigned char usb_address;
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unsigned req_pending:1, req_std:1, req_config:1;
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};
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extern struct lh7a40x_udc *the_controller;
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#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
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#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
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#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
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#endif
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