Imre Deak bfafe93a1c drm/i915: cache hw power well enabled state ... Jesse noticed that the punit communication needed to query the VLV power well status can cause substantial delays. Since we can query the state frequently, for example during I2C transfers, maintain a cached version of the HW state to get rid of this delay. This fixes at least one reported regression where boot time increased by ~4 seconds due to frequent power well state queries on VLV during eDP EDID read. This regression has been introduced in commit bb4932c4f1 Author: Imre Deak <imre.deak@intel.com> Date: Mon Apr 14 20:24:33 2014 +0300 drm/i915: vlv: check port power domain instead of only D0 for eDP VDD on Reported-by: Jesse Barnes <jesse.barnes@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2014-06-23 10:02:03 +03:00
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drm	drm/i915: cache hw power well enabled state	2014-06-23 10:02:03 +03:00
host1x	gpu: host1x: Rename internal functions for clarity	2014-06-05 23:10:30 +02:00
ipu-v3	Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux	2014-06-12 11:32:30 -07:00
vga	vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled	2014-06-02 10:25:08 -04:00
Makefile	gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging	2014-06-04 11:06:52 +02:00