543 lines
15 KiB
C
543 lines
15 KiB
C
#ifndef TLAN_H
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#define TLAN_H
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/********************************************************************
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*
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* Linux ThunderLAN Driver
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*
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* tlan.h
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* by James Banks
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*
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* (C) 1997-1998 Caldera, Inc.
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* (C) 1999-2001 Torben Mathiasen
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*
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* Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com>
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* New Maintainer
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*
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********************************************************************/
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#include <asm/io.h>
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#include <asm/types.h>
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#include <linux/netdevice.h>
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/*****************************************************************
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* TLan Definitions
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*
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****************************************************************/
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#define TLAN_MIN_FRAME_SIZE 64
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#define TLAN_MAX_FRAME_SIZE 1600
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#define TLAN_NUM_RX_LISTS 32
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#define TLAN_NUM_TX_LISTS 64
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#define TLAN_IGNORE 0
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#define TLAN_RECORD 1
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#define TLAN_DBG(lvl, format, args...) \
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do { if (debug&lvl) printk(KERN_DEBUG "TLAN: " format, ##args ); } while(0)
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#define TLAN_DEBUG_GNRL 0x0001
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#define TLAN_DEBUG_TX 0x0002
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#define TLAN_DEBUG_RX 0x0004
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#define TLAN_DEBUG_LIST 0x0008
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#define TLAN_DEBUG_PROBE 0x0010
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#define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */
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#define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */
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/*****************************************************************
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* Device Identification Definitions
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*
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****************************************************************/
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#define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
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#define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
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#ifndef PCI_DEVICE_ID_OLICOM_OC2183
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#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
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#endif
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#ifndef PCI_DEVICE_ID_OLICOM_OC2325
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#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
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#endif
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#ifndef PCI_DEVICE_ID_OLICOM_OC2326
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#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
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#endif
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typedef struct tlan_adapter_entry {
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u16 vendorId;
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u16 deviceId;
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char *deviceLabel;
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u32 flags;
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u16 addrOfs;
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} TLanAdapterEntry;
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#define TLAN_ADAPTER_NONE 0x00000000
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#define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
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#define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
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#define TLAN_ADAPTER_USE_INTERN_10 0x00000004
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#define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
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#define TLAN_SPEED_DEFAULT 0
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#define TLAN_SPEED_10 10
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#define TLAN_SPEED_100 100
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#define TLAN_DUPLEX_DEFAULT 0
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#define TLAN_DUPLEX_HALF 1
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#define TLAN_DUPLEX_FULL 2
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/*****************************************************************
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* EISA Definitions
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*
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****************************************************************/
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#define EISA_ID 0xc80 /* EISA ID Registers */
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#define EISA_ID0 0xc80 /* EISA ID Register 0 */
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#define EISA_ID1 0xc81 /* EISA ID Register 1 */
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#define EISA_ID2 0xc82 /* EISA ID Register 2 */
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#define EISA_ID3 0xc83 /* EISA ID Register 3 */
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#define EISA_CR 0xc84 /* EISA Control Register */
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#define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
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#define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
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#define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
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#define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
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#define EISA_APROM 0xc90 /* Ethernet Address PROM */
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/*****************************************************************
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* Rx/Tx List Definitions
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*
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****************************************************************/
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#define TLAN_BUFFERS_PER_LIST 10
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#define TLAN_LAST_BUFFER 0x80000000
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#define TLAN_CSTAT_UNUSED 0x8000
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#define TLAN_CSTAT_FRM_CMP 0x4000
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#define TLAN_CSTAT_READY 0x3000
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#define TLAN_CSTAT_EOC 0x0800
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#define TLAN_CSTAT_RX_ERROR 0x0400
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#define TLAN_CSTAT_PASS_CRC 0x0200
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#define TLAN_CSTAT_DP_PR 0x0100
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typedef struct tlan_buffer_ref_tag {
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u32 count;
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u32 address;
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} TLanBufferRef;
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typedef struct tlan_list_tag {
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u32 forward;
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u16 cStat;
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u16 frameSize;
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TLanBufferRef buffer[TLAN_BUFFERS_PER_LIST];
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} TLanList;
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typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
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/*****************************************************************
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* PHY definitions
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*
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****************************************************************/
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#define TLAN_PHY_MAX_ADDR 0x1F
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#define TLAN_PHY_NONE 0x20
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/*****************************************************************
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* TLAN Private Information Structure
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*
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****************************************************************/
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typedef struct tlan_private_tag {
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struct net_device *nextDevice;
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struct pci_dev *pciDev;
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struct net_device *dev;
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void *dmaStorage;
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dma_addr_t dmaStorageDMA;
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unsigned int dmaSize;
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u8 *padBuffer;
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TLanList *rxList;
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dma_addr_t rxListDMA;
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u8 *rxBuffer;
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dma_addr_t rxBufferDMA;
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u32 rxHead;
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u32 rxTail;
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u32 rxEocCount;
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TLanList *txList;
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dma_addr_t txListDMA;
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u8 *txBuffer;
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dma_addr_t txBufferDMA;
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u32 txHead;
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u32 txInProgress;
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u32 txTail;
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u32 txBusyCount;
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u32 phyOnline;
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u32 timerSetAt;
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u32 timerType;
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struct timer_list timer;
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struct board *adapter;
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u32 adapterRev;
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u32 aui;
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u32 debug;
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u32 duplex;
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u32 phy[2];
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u32 phyNum;
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u32 speed;
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u8 tlanRev;
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u8 tlanFullDuplex;
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spinlock_t lock;
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u8 link;
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u8 is_eisa;
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struct work_struct tlan_tqueue;
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u8 neg_be_verbose;
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} TLanPrivateInfo;
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/*****************************************************************
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* TLan Driver Timer Definitions
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*
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****************************************************************/
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#define TLAN_TIMER_LINK_BEAT 1
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#define TLAN_TIMER_ACTIVITY 2
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#define TLAN_TIMER_PHY_PDOWN 3
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#define TLAN_TIMER_PHY_PUP 4
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#define TLAN_TIMER_PHY_RESET 5
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#define TLAN_TIMER_PHY_START_LINK 6
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#define TLAN_TIMER_PHY_FINISH_AN 7
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#define TLAN_TIMER_FINISH_RESET 8
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#define TLAN_TIMER_ACT_DELAY (HZ/10)
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/*****************************************************************
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* TLan Driver Eeprom Definitions
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*
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****************************************************************/
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#define TLAN_EEPROM_ACK 0
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#define TLAN_EEPROM_STOP 1
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/*****************************************************************
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* Host Register Offsets and Contents
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*
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****************************************************************/
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#define TLAN_HOST_CMD 0x00
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#define TLAN_HC_GO 0x80000000
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#define TLAN_HC_STOP 0x40000000
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#define TLAN_HC_ACK 0x20000000
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#define TLAN_HC_CS_MASK 0x1FE00000
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#define TLAN_HC_EOC 0x00100000
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#define TLAN_HC_RT 0x00080000
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#define TLAN_HC_NES 0x00040000
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#define TLAN_HC_AD_RST 0x00008000
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#define TLAN_HC_LD_TMR 0x00004000
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#define TLAN_HC_LD_THR 0x00002000
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#define TLAN_HC_REQ_INT 0x00001000
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#define TLAN_HC_INT_OFF 0x00000800
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#define TLAN_HC_INT_ON 0x00000400
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#define TLAN_HC_AC_MASK 0x000000FF
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#define TLAN_CH_PARM 0x04
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#define TLAN_DIO_ADR 0x08
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#define TLAN_DA_ADR_INC 0x8000
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#define TLAN_DA_RAM_ADR 0x4000
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#define TLAN_HOST_INT 0x0A
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#define TLAN_HI_IV_MASK 0x1FE0
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#define TLAN_HI_IT_MASK 0x001C
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#define TLAN_DIO_DATA 0x0C
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/* ThunderLAN Internal Register DIO Offsets */
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#define TLAN_NET_CMD 0x00
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#define TLAN_NET_CMD_NRESET 0x80
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#define TLAN_NET_CMD_NWRAP 0x40
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#define TLAN_NET_CMD_CSF 0x20
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#define TLAN_NET_CMD_CAF 0x10
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#define TLAN_NET_CMD_NOBRX 0x08
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#define TLAN_NET_CMD_DUPLEX 0x04
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#define TLAN_NET_CMD_TRFRAM 0x02
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#define TLAN_NET_CMD_TXPACE 0x01
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#define TLAN_NET_SIO 0x01
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#define TLAN_NET_SIO_MINTEN 0x80
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#define TLAN_NET_SIO_ECLOK 0x40
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#define TLAN_NET_SIO_ETXEN 0x20
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#define TLAN_NET_SIO_EDATA 0x10
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#define TLAN_NET_SIO_NMRST 0x08
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#define TLAN_NET_SIO_MCLK 0x04
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#define TLAN_NET_SIO_MTXEN 0x02
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#define TLAN_NET_SIO_MDATA 0x01
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#define TLAN_NET_STS 0x02
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#define TLAN_NET_STS_MIRQ 0x80
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#define TLAN_NET_STS_HBEAT 0x40
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#define TLAN_NET_STS_TXSTOP 0x20
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#define TLAN_NET_STS_RXSTOP 0x10
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#define TLAN_NET_STS_RSRVD 0x0F
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#define TLAN_NET_MASK 0x03
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#define TLAN_NET_MASK_MASK7 0x80
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#define TLAN_NET_MASK_MASK6 0x40
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#define TLAN_NET_MASK_MASK5 0x20
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#define TLAN_NET_MASK_MASK4 0x10
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#define TLAN_NET_MASK_RSRVD 0x0F
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#define TLAN_NET_CONFIG 0x04
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#define TLAN_NET_CFG_RCLK 0x8000
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#define TLAN_NET_CFG_TCLK 0x4000
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#define TLAN_NET_CFG_BIT 0x2000
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#define TLAN_NET_CFG_RXCRC 0x1000
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#define TLAN_NET_CFG_PEF 0x0800
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#define TLAN_NET_CFG_1FRAG 0x0400
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#define TLAN_NET_CFG_1CHAN 0x0200
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#define TLAN_NET_CFG_MTEST 0x0100
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#define TLAN_NET_CFG_PHY_EN 0x0080
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#define TLAN_NET_CFG_MSMASK 0x007F
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#define TLAN_MAN_TEST 0x06
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#define TLAN_DEF_VENDOR_ID 0x08
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#define TLAN_DEF_DEVICE_ID 0x0A
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#define TLAN_DEF_REVISION 0x0C
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#define TLAN_DEF_SUBCLASS 0x0D
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#define TLAN_DEF_MIN_LAT 0x0E
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#define TLAN_DEF_MAX_LAT 0x0F
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#define TLAN_AREG_0 0x10
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#define TLAN_AREG_1 0x16
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#define TLAN_AREG_2 0x1C
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#define TLAN_AREG_3 0x22
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#define TLAN_HASH_1 0x28
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#define TLAN_HASH_2 0x2C
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#define TLAN_GOOD_TX_FRMS 0x30
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#define TLAN_TX_UNDERUNS 0x33
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#define TLAN_GOOD_RX_FRMS 0x34
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#define TLAN_RX_OVERRUNS 0x37
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#define TLAN_DEFERRED_TX 0x38
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#define TLAN_CRC_ERRORS 0x3A
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#define TLAN_CODE_ERRORS 0x3B
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#define TLAN_MULTICOL_FRMS 0x3C
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#define TLAN_SINGLECOL_FRMS 0x3E
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#define TLAN_EXCESSCOL_FRMS 0x40
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#define TLAN_LATE_COLS 0x41
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#define TLAN_CARRIER_LOSS 0x42
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#define TLAN_ACOMMIT 0x43
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#define TLAN_LED_REG 0x44
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#define TLAN_LED_ACT 0x10
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#define TLAN_LED_LINK 0x01
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#define TLAN_BSIZE_REG 0x45
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#define TLAN_MAX_RX 0x46
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#define TLAN_INT_DIS 0x48
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#define TLAN_ID_TX_EOC 0x04
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#define TLAN_ID_RX_EOF 0x02
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#define TLAN_ID_RX_EOC 0x01
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/* ThunderLAN Interrupt Codes */
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#define TLAN_INT_NUMBER_OF_INTS 8
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#define TLAN_INT_NONE 0x0000
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#define TLAN_INT_TX_EOF 0x0001
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#define TLAN_INT_STAT_OVERFLOW 0x0002
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#define TLAN_INT_RX_EOF 0x0003
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#define TLAN_INT_DUMMY 0x0004
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#define TLAN_INT_TX_EOC 0x0005
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#define TLAN_INT_STATUS_CHECK 0x0006
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#define TLAN_INT_RX_EOC 0x0007
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/* ThunderLAN MII Registers */
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/* Generic MII/PHY Registers */
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#define MII_GEN_CTL 0x00
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#define MII_GC_RESET 0x8000
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#define MII_GC_LOOPBK 0x4000
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#define MII_GC_SPEEDSEL 0x2000
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#define MII_GC_AUTOENB 0x1000
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#define MII_GC_PDOWN 0x0800
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#define MII_GC_ISOLATE 0x0400
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#define MII_GC_AUTORSRT 0x0200
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#define MII_GC_DUPLEX 0x0100
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#define MII_GC_COLTEST 0x0080
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#define MII_GC_RESERVED 0x007F
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#define MII_GEN_STS 0x01
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#define MII_GS_100BT4 0x8000
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#define MII_GS_100BTXFD 0x4000
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#define MII_GS_100BTXHD 0x2000
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#define MII_GS_10BTFD 0x1000
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#define MII_GS_10BTHD 0x0800
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#define MII_GS_RESERVED 0x07C0
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#define MII_GS_AUTOCMPLT 0x0020
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#define MII_GS_RFLT 0x0010
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#define MII_GS_AUTONEG 0x0008
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#define MII_GS_LINK 0x0004
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#define MII_GS_JABBER 0x0002
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#define MII_GS_EXTCAP 0x0001
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#define MII_GEN_ID_HI 0x02
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#define MII_GEN_ID_LO 0x03
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#define MII_GIL_OUI 0xFC00
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#define MII_GIL_MODEL 0x03F0
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#define MII_GIL_REVISION 0x000F
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#define MII_AN_ADV 0x04
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#define MII_AN_LPA 0x05
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#define MII_AN_EXP 0x06
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/* ThunderLAN Specific MII/PHY Registers */
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#define TLAN_TLPHY_ID 0x10
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#define TLAN_TLPHY_CTL 0x11
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#define TLAN_TC_IGLINK 0x8000
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#define TLAN_TC_SWAPOL 0x4000
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#define TLAN_TC_AUISEL 0x2000
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#define TLAN_TC_SQEEN 0x1000
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#define TLAN_TC_MTEST 0x0800
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#define TLAN_TC_RESERVED 0x07F8
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#define TLAN_TC_NFEW 0x0004
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#define TLAN_TC_INTEN 0x0002
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#define TLAN_TC_TINT 0x0001
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#define TLAN_TLPHY_STS 0x12
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#define TLAN_TS_MINT 0x8000
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#define TLAN_TS_PHOK 0x4000
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#define TLAN_TS_POLOK 0x2000
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#define TLAN_TS_TPENERGY 0x1000
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#define TLAN_TS_RESERVED 0x0FFF
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#define TLAN_TLPHY_PAR 0x19
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#define TLAN_PHY_CIM_STAT 0x0020
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#define TLAN_PHY_SPEED_100 0x0040
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#define TLAN_PHY_DUPLEX_FULL 0x0080
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#define TLAN_PHY_AN_EN_STAT 0x0400
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/* National Sem. & Level1 PHY id's */
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#define NAT_SEM_ID1 0x2000
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#define NAT_SEM_ID2 0x5C01
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#define LEVEL1_ID1 0x7810
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#define LEVEL1_ID2 0x0000
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#define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
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/* Routines to access internal registers. */
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static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
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{
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outw(internal_addr, base_addr + TLAN_DIO_ADR);
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return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
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} /* TLan_DioRead8 */
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static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
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{
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outw(internal_addr, base_addr + TLAN_DIO_ADR);
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return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
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} /* TLan_DioRead16 */
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static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
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{
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outw(internal_addr, base_addr + TLAN_DIO_ADR);
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return (inl(base_addr + TLAN_DIO_DATA));
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} /* TLan_DioRead32 */
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static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
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{
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outw(internal_addr, base_addr + TLAN_DIO_ADR);
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outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
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}
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static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
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{
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outw(internal_addr, base_addr + TLAN_DIO_ADR);
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outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
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}
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static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
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{
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outw(internal_addr, base_addr + TLAN_DIO_ADR);
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outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
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}
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#define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port)
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#define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit))
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#define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port)
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|
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/*
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* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those
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|
* the code below is about seven times as fast as the original code
|
|
*
|
|
* The original code was:
|
|
*
|
|
* u32 xor( u32 a, u32 b ) { return ( ( a && ! b ) || ( ! a && b ) ); }
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|
*
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|
* #define XOR8( a, b, c, d, e, f, g, h ) \
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* xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
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|
* #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
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|
*
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* hash = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24),
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* DA(a,30), DA(a,36), DA(a,42) );
|
|
* hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25),
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* DA(a,31), DA(a,37), DA(a,43) ) << 1;
|
|
* hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26),
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* DA(a,32), DA(a,38), DA(a,44) ) << 2;
|
|
* hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27),
|
|
* DA(a,33), DA(a,39), DA(a,45) ) << 3;
|
|
* hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28),
|
|
* DA(a,34), DA(a,40), DA(a,46) ) << 4;
|
|
* hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29),
|
|
* DA(a,35), DA(a,41), DA(a,47) ) << 5;
|
|
*
|
|
*/
|
|
static inline u32 TLan_HashFunc( const u8 *a )
|
|
{
|
|
u8 hash;
|
|
|
|
hash = (a[0]^a[3]); /* & 077 */
|
|
hash ^= ((a[0]^a[3])>>6); /* & 003 */
|
|
hash ^= ((a[1]^a[4])<<2); /* & 074 */
|
|
hash ^= ((a[1]^a[4])>>4); /* & 017 */
|
|
hash ^= ((a[2]^a[5])<<4); /* & 060 */
|
|
hash ^= ((a[2]^a[5])>>2); /* & 077 */
|
|
|
|
return (hash & 077);
|
|
}
|
|
#endif
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