747 lines
21 KiB
C
747 lines
21 KiB
C
/*
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* U300 clock implementation
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* Copyright (C) 2007-2012 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <mach/syscon.h>
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/*
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* The clocking hierarchy currently looks like this.
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* NOTE: the idea is NOT to show how the clocks are routed on the chip!
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* The ideas is to show dependencies, so a clock higher up in the
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* hierarchy has to be on in order for another clock to be on. Now,
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* both CPU and DMA can actually be on top of the hierarchy, and that
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* is not modeled currently. Instead we have the backbone AMBA bus on
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* top. This bus cannot be programmed in any way but conceptually it
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* needs to be active for the bridges and devices to transport data.
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*
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* Please be aware that a few clocks are hw controlled, which mean that
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* the hw itself can turn on/off or change the rate of the clock when
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* needed!
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*
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* AMBA bus
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* |
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* +- CPU
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* +- FSMC NANDIF NAND Flash interface
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* +- SEMI Shared Memory interface
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* +- ISP Image Signal Processor (U335 only)
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* +- CDS (U335 only)
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* +- DMA Direct Memory Access Controller
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* +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
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* +- APEX
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* +- VIDEO_ENC AVE2/3 Video Encoder
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* +- XGAM Graphics Accelerator Controller
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* +- AHB
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* |
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* +- ahb:0 AHB Bridge
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* | |
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* | +- ahb:1 INTCON Interrupt controller
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* | +- ahb:3 MSPRO Memory Stick Pro controller
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* | +- ahb:4 EMIF External Memory interface
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* |
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* +- fast:0 FAST bridge
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* | |
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* | +- fast:1 MMCSD MMC/SD card reader controller
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* | +- fast:2 I2S0 PCM I2S channel 0 controller
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* | +- fast:3 I2S1 PCM I2S channel 1 controller
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* | +- fast:4 I2C0 I2C channel 0 controller
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* | +- fast:5 I2C1 I2C channel 1 controller
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* | +- fast:6 SPI SPI controller
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* | +- fast:7 UART1 Secondary UART (U335 only)
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* |
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* +- slow:0 SLOW bridge
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* |
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* +- slow:1 SYSCON (not possible to control)
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* +- slow:2 WDOG Watchdog
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* +- slow:3 UART0 primary UART
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* +- slow:4 TIMER_APP Application timer - used in Linux
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* +- slow:5 KEYPAD controller
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* +- slow:6 GPIO controller
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* +- slow:7 RTC controller
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* +- slow:8 BT Bus Tracer (not used currently)
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* +- slow:9 EH Event Handler (not used currently)
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* +- slow:a TIMER_ACC Access style timer (not used currently)
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* +- slow:b PPM (U335 only, what is that?)
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*/
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/* Global syscon virtual base */
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static void __iomem *syscon_vbase;
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/**
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* struct clk_syscon - U300 syscon clock
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* @hw: corresponding clock hardware entry
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* @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
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* and does not need any magic pokes to be enabled/disabled
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* @reset: state holder, whether this block's reset line is asserted or not
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* @res_reg: reset line enable/disable flag register
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* @res_bit: bit for resetting or taking this consumer out of reset
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* @en_reg: clock line enable/disable flag register
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* @en_bit: bit for enabling/disabling this consumer clock line
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* @clk_val: magic value to poke in the register to enable/disable
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* this one clock
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*/
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struct clk_syscon {
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struct clk_hw hw;
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bool hw_ctrld;
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bool reset;
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void __iomem *res_reg;
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u8 res_bit;
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void __iomem *en_reg;
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u8 en_bit;
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u16 clk_val;
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};
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#define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
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static DEFINE_SPINLOCK(syscon_resetreg_lock);
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/*
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* Reset control functions. We remember if a block has been
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* taken out of reset and don't remove the reset assertion again
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* and vice versa. Currently we only remove resets so the
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* enablement function is defined out.
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*/
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static void syscon_block_reset_enable(struct clk_syscon *sclk)
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{
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unsigned long iflags;
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u16 val;
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/* Not all blocks support resetting */
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if (!sclk->res_reg)
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return;
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spin_lock_irqsave(&syscon_resetreg_lock, iflags);
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val = readw(sclk->res_reg);
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val |= BIT(sclk->res_bit);
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writew(val, sclk->res_reg);
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spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
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sclk->reset = true;
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}
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static void syscon_block_reset_disable(struct clk_syscon *sclk)
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{
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unsigned long iflags;
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u16 val;
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/* Not all blocks support resetting */
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if (!sclk->res_reg)
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return;
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spin_lock_irqsave(&syscon_resetreg_lock, iflags);
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val = readw(sclk->res_reg);
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val &= ~BIT(sclk->res_bit);
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writew(val, sclk->res_reg);
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spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
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sclk->reset = false;
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}
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static int syscon_clk_prepare(struct clk_hw *hw)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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/* If the block is in reset, bring it out */
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if (sclk->reset)
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syscon_block_reset_disable(sclk);
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return 0;
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}
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static void syscon_clk_unprepare(struct clk_hw *hw)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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/* Please don't force the console into reset */
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if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
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return;
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/* When unpreparing, force block into reset */
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if (!sclk->reset)
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syscon_block_reset_enable(sclk);
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}
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static int syscon_clk_enable(struct clk_hw *hw)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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/* Don't touch the hardware controlled clocks */
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if (sclk->hw_ctrld)
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return 0;
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/* These cannot be controlled */
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if (sclk->clk_val == 0xFFFFU)
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return 0;
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writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
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return 0;
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}
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static void syscon_clk_disable(struct clk_hw *hw)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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/* Don't touch the hardware controlled clocks */
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if (sclk->hw_ctrld)
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return;
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if (sclk->clk_val == 0xFFFFU)
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return;
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/* Please don't disable the console port */
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if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
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return;
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writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
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}
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static int syscon_clk_is_enabled(struct clk_hw *hw)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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u16 val;
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/* If no enable register defined, it's always-on */
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if (!sclk->en_reg)
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return 1;
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val = readw(sclk->en_reg);
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val &= BIT(sclk->en_bit);
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return val ? 1 : 0;
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}
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static u16 syscon_get_perf(void)
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{
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u16 val;
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val = readw(syscon_vbase + U300_SYSCON_CCR);
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val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
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return val;
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}
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static unsigned long
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syscon_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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u16 perf = syscon_get_perf();
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switch(sclk->clk_val) {
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case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
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case U300_SYSCON_SBCER_I2C0_CLK_EN:
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case U300_SYSCON_SBCER_I2C1_CLK_EN:
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case U300_SYSCON_SBCER_MMC_CLK_EN:
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case U300_SYSCON_SBCER_SPI_CLK_EN:
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/* The FAST clocks have one progression */
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switch(perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 13000000;
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default:
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return parent_rate; /* 26 MHz */
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}
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case U300_SYSCON_SBCER_DMAC_CLK_EN:
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case U300_SYSCON_SBCER_NANDIF_CLK_EN:
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case U300_SYSCON_SBCER_XGAM_CLK_EN:
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/* AMBA interconnect peripherals */
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switch(perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 6500000;
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
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return 26000000;
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default:
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return parent_rate; /* 52 MHz */
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}
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case U300_SYSCON_SBCER_SEMI_CLK_EN:
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case U300_SYSCON_SBCER_EMIF_CLK_EN:
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/* EMIF speeds */
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switch(perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 13000000;
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
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return 52000000;
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default:
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return 104000000;
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}
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case U300_SYSCON_SBCER_CPU_CLK_EN:
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/* And the fast CPU clock */
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switch(perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 13000000;
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
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return 52000000;
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
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return 104000000;
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default:
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return parent_rate; /* 208 MHz */
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}
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default:
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/*
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* The SLOW clocks and default just inherit the rate of
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* their parent (typically PLL13 13 MHz).
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*/
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return parent_rate;
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}
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}
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static long
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syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
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return *prate;
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/* We really only support setting the rate of the CPU clock */
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if (rate <= 13000000)
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return 13000000;
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if (rate <= 52000000)
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return 52000000;
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if (rate <= 104000000)
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return 104000000;
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return 208000000;
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}
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static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_syscon *sclk = to_syscon(hw);
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u16 val;
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/* We only support setting the rate of the CPU clock */
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if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
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return -EINVAL;
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switch (rate) {
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case 13000000:
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val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
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break;
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case 52000000:
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val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
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break;
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case 104000000:
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val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
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break;
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case 208000000:
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val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
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break;
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default:
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return -EINVAL;
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}
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val |= readw(syscon_vbase + U300_SYSCON_CCR) &
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~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
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writew(val, syscon_vbase + U300_SYSCON_CCR);
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return 0;
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}
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static const struct clk_ops syscon_clk_ops = {
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.prepare = syscon_clk_prepare,
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.unprepare = syscon_clk_unprepare,
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.enable = syscon_clk_enable,
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.disable = syscon_clk_disable,
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.is_enabled = syscon_clk_is_enabled,
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.recalc_rate = syscon_clk_recalc_rate,
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.round_rate = syscon_clk_round_rate,
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.set_rate = syscon_clk_set_rate,
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};
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static struct clk * __init
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syscon_clk_register(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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bool hw_ctrld,
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void __iomem *res_reg, u8 res_bit,
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void __iomem *en_reg, u8 en_bit,
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u16 clk_val)
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{
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struct clk *clk;
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struct clk_syscon *sclk;
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struct clk_init_data init;
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sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL);
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if (!sclk) {
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pr_err("could not allocate syscon clock %s\n",
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name);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &syscon_clk_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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sclk->hw.init = &init;
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sclk->hw_ctrld = hw_ctrld;
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/* Assume the block is in reset at registration */
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sclk->reset = true;
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sclk->res_reg = res_reg;
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sclk->res_bit = res_bit;
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sclk->en_reg = en_reg;
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sclk->en_bit = en_bit;
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sclk->clk_val = clk_val;
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clk = clk_register(dev, &sclk->hw);
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if (IS_ERR(clk))
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kfree(sclk);
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return clk;
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}
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/**
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* struct clk_mclk - U300 MCLK clock (MMC/SD clock)
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* @hw: corresponding clock hardware entry
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* @is_mspro: if this is the memory stick clock rather than MMC/SD
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*/
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struct clk_mclk {
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struct clk_hw hw;
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bool is_mspro;
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};
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#define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
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static int mclk_clk_prepare(struct clk_hw *hw)
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{
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struct clk_mclk *mclk = to_mclk(hw);
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u16 val;
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/* The MMC and MSPRO clocks need some special set-up */
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if (!mclk->is_mspro) {
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/* Set default MMC clock divisor to 18.9 MHz */
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writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
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val = readw(syscon_vbase + U300_SYSCON_MMCR);
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/* Disable the MMC feedback clock */
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val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
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/* Disable MSPRO frequency */
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val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
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writew(val, syscon_vbase + U300_SYSCON_MMCR);
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} else {
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val = readw(syscon_vbase + U300_SYSCON_MMCR);
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/* Disable the MMC feedback clock */
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val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
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/* Enable MSPRO frequency */
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val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
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writew(val, syscon_vbase + U300_SYSCON_MMCR);
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}
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return 0;
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}
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static unsigned long
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mclk_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u16 perf = syscon_get_perf();
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switch (perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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/*
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* Here, the 208 MHz PLL gets shut down and the always
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* on 13 MHz PLL used for RTC etc kicks into use
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* instead.
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*/
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return 13000000;
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
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{
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/*
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* This clock is under program control. The register is
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* divided in two nybbles, bit 7-4 gives cycles-1 to count
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* high, bit 3-0 gives cycles-1 to count low. Distribute
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* these with no more than 1 cycle difference between
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* low and high and add low and high to get the actual
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* divisor. The base PLL is 208 MHz. Writing 0x00 will
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* divide by 1 and 1 so the highest frequency possible
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* is 104 MHz.
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*
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* e.g. 0x54 =>
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* f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
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*/
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u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
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U300_SYSCON_MMF0R_MASK;
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switch (val) {
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case 0x0054:
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return 18900000;
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case 0x0044:
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return 20800000;
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case 0x0043:
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return 23100000;
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case 0x0033:
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return 26000000;
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case 0x0032:
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return 29700000;
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case 0x0022:
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return 34700000;
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case 0x0021:
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return 41600000;
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case 0x0011:
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return 52000000;
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case 0x0000:
|
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return 104000000;
|
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default:
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break;
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}
|
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}
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|
default:
|
|
break;
|
|
}
|
|
return parent_rate;
|
|
}
|
|
|
|
static long
|
|
mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate)
|
|
{
|
|
if (rate <= 18900000)
|
|
return 18900000;
|
|
if (rate <= 20800000)
|
|
return 20800000;
|
|
if (rate <= 23100000)
|
|
return 23100000;
|
|
if (rate <= 26000000)
|
|
return 26000000;
|
|
if (rate <= 29700000)
|
|
return 29700000;
|
|
if (rate <= 34700000)
|
|
return 34700000;
|
|
if (rate <= 41600000)
|
|
return 41600000;
|
|
/* Highest rate */
|
|
return 52000000;
|
|
}
|
|
|
|
static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
u16 val;
|
|
u16 reg;
|
|
|
|
switch (rate) {
|
|
case 18900000:
|
|
val = 0x0054;
|
|
break;
|
|
case 20800000:
|
|
val = 0x0044;
|
|
break;
|
|
case 23100000:
|
|
val = 0x0043;
|
|
break;
|
|
case 26000000:
|
|
val = 0x0033;
|
|
break;
|
|
case 29700000:
|
|
val = 0x0032;
|
|
break;
|
|
case 34700000:
|
|
val = 0x0022;
|
|
break;
|
|
case 41600000:
|
|
val = 0x0021;
|
|
break;
|
|
case 52000000:
|
|
val = 0x0011;
|
|
break;
|
|
case 104000000:
|
|
val = 0x0000;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
|
|
~U300_SYSCON_MMF0R_MASK;
|
|
writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
|
|
return 0;
|
|
}
|
|
|
|
static const struct clk_ops mclk_ops = {
|
|
.prepare = mclk_clk_prepare,
|
|
.recalc_rate = mclk_clk_recalc_rate,
|
|
.round_rate = mclk_clk_round_rate,
|
|
.set_rate = mclk_clk_set_rate,
|
|
};
|
|
|
|
static struct clk * __init
|
|
mclk_clk_register(struct device *dev, const char *name,
|
|
const char *parent_name, bool is_mspro)
|
|
{
|
|
struct clk *clk;
|
|
struct clk_mclk *mclk;
|
|
struct clk_init_data init;
|
|
|
|
mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL);
|
|
if (!mclk) {
|
|
pr_err("could not allocate MMC/SD clock %s\n",
|
|
name);
|
|
return ERR_PTR(-ENOMEM);
|
|
}
|
|
init.name = "mclk";
|
|
init.ops = &mclk_ops;
|
|
init.flags = 0;
|
|
init.parent_names = (parent_name ? &parent_name : NULL);
|
|
init.num_parents = (parent_name ? 1 : 0);
|
|
mclk->hw.init = &init;
|
|
mclk->is_mspro = is_mspro;
|
|
|
|
clk = clk_register(dev, &mclk->hw);
|
|
if (IS_ERR(clk))
|
|
kfree(mclk);
|
|
|
|
return clk;
|
|
}
|
|
|
|
void __init u300_clk_init(void __iomem *base)
|
|
{
|
|
u16 val;
|
|
struct clk *clk;
|
|
|
|
syscon_vbase = base;
|
|
|
|
/* Set system to run at PLL208, max performance, a known state. */
|
|
val = readw(syscon_vbase + U300_SYSCON_CCR);
|
|
val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
|
|
writew(val, syscon_vbase + U300_SYSCON_CCR);
|
|
/* Wait for the PLL208 to lock if not locked in yet */
|
|
while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
|
|
U300_SYSCON_CSR_PLL208_LOCK_IND));
|
|
|
|
/* Power management enable */
|
|
val = readw(syscon_vbase + U300_SYSCON_PMCR);
|
|
val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
|
|
writew(val, syscon_vbase + U300_SYSCON_PMCR);
|
|
|
|
/* These are always available (RTC and PLL13) */
|
|
clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
|
|
CLK_IS_ROOT, 32768);
|
|
/* The watchdog sits directly on the 32 kHz clock */
|
|
clk_register_clkdev(clk, NULL, "coh901327_wdog");
|
|
clk = clk_register_fixed_rate(NULL, "pll13", NULL,
|
|
CLK_IS_ROOT, 13000000);
|
|
|
|
/* These derive from PLL208 */
|
|
clk = clk_register_fixed_rate(NULL, "pll208", NULL,
|
|
CLK_IS_ROOT, 208000000);
|
|
clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
|
|
0, 1, 1);
|
|
clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
|
|
0, 1, 2);
|
|
clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
|
|
0, 1, 4);
|
|
/* The 52 MHz is divided down to 26 MHz */
|
|
clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
|
|
0, 1, 2);
|
|
|
|
/* Directly on the AMBA interconnect */
|
|
clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
|
|
syscon_vbase + U300_SYSCON_RRR, 3,
|
|
syscon_vbase + U300_SYSCON_CERR, 3,
|
|
U300_SYSCON_SBCER_CPU_CLK_EN);
|
|
clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
|
|
syscon_vbase + U300_SYSCON_RRR, 4,
|
|
syscon_vbase + U300_SYSCON_CERR, 4,
|
|
U300_SYSCON_SBCER_DMAC_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "dma");
|
|
clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RRR, 6,
|
|
syscon_vbase + U300_SYSCON_CERR, 6,
|
|
U300_SYSCON_SBCER_NANDIF_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "fsmc-nand");
|
|
clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
|
|
syscon_vbase + U300_SYSCON_RRR, 8,
|
|
syscon_vbase + U300_SYSCON_CERR, 8,
|
|
U300_SYSCON_SBCER_XGAM_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "xgam");
|
|
clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RRR, 9,
|
|
syscon_vbase + U300_SYSCON_CERR, 9,
|
|
U300_SYSCON_SBCER_SEMI_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "semi");
|
|
|
|
/* AHB bridge clocks */
|
|
clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
|
|
syscon_vbase + U300_SYSCON_RRR, 10,
|
|
syscon_vbase + U300_SYSCON_CERR, 10,
|
|
U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
|
|
clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RRR, 12,
|
|
syscon_vbase + U300_SYSCON_CERR, 12,
|
|
/* Cannot be enabled, just taken out of reset */
|
|
0xFFFFU);
|
|
clk_register_clkdev(clk, NULL, "intcon");
|
|
clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RRR, 5,
|
|
syscon_vbase + U300_SYSCON_CERR, 5,
|
|
U300_SYSCON_SBCER_EMIF_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "pl172");
|
|
|
|
/* FAST bridge clocks */
|
|
clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
|
|
syscon_vbase + U300_SYSCON_RFR, 0,
|
|
syscon_vbase + U300_SYSCON_CEFR, 0,
|
|
U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
|
|
clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RFR, 1,
|
|
syscon_vbase + U300_SYSCON_CEFR, 1,
|
|
U300_SYSCON_SBCER_I2C0_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "stu300.0");
|
|
clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RFR, 2,
|
|
syscon_vbase + U300_SYSCON_CEFR, 2,
|
|
U300_SYSCON_SBCER_I2C1_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "stu300.1");
|
|
clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RFR, 5,
|
|
syscon_vbase + U300_SYSCON_CEFR, 5,
|
|
U300_SYSCON_SBCER_MMC_CLK_EN);
|
|
clk_register_clkdev(clk, "apb_pclk", "mmci");
|
|
clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RFR, 6,
|
|
syscon_vbase + U300_SYSCON_CEFR, 6,
|
|
U300_SYSCON_SBCER_SPI_CLK_EN);
|
|
/* The SPI has no external clock for the outward bus, uses the pclk */
|
|
clk_register_clkdev(clk, NULL, "pl022");
|
|
clk_register_clkdev(clk, "apb_pclk", "pl022");
|
|
|
|
/* SLOW bridge clocks */
|
|
clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
|
|
syscon_vbase + U300_SYSCON_RSR, 0,
|
|
syscon_vbase + U300_SYSCON_CESR, 0,
|
|
U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
|
|
clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RSR, 1,
|
|
syscon_vbase + U300_SYSCON_CESR, 1,
|
|
U300_SYSCON_SBCER_UART_CLK_EN);
|
|
/* Same clock is used for APB and outward bus */
|
|
clk_register_clkdev(clk, NULL, "uart0");
|
|
clk_register_clkdev(clk, "apb_pclk", "uart0");
|
|
clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RSR, 4,
|
|
syscon_vbase + U300_SYSCON_CESR, 4,
|
|
U300_SYSCON_SBCER_GPIO_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "u300-gpio");
|
|
clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RSR, 5,
|
|
syscon_vbase + U300_SYSCON_CESR, 6,
|
|
U300_SYSCON_SBCER_KEYPAD_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "coh901461-keypad");
|
|
clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
|
|
syscon_vbase + U300_SYSCON_RSR, 6,
|
|
/* No clock enable register bit */
|
|
NULL, 0, 0xFFFFU);
|
|
clk_register_clkdev(clk, NULL, "rtc-coh901331");
|
|
clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RSR, 7,
|
|
syscon_vbase + U300_SYSCON_CESR, 7,
|
|
U300_SYSCON_SBCER_APP_TMR_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "apptimer");
|
|
clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
|
|
syscon_vbase + U300_SYSCON_RSR, 8,
|
|
syscon_vbase + U300_SYSCON_CESR, 8,
|
|
U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
|
|
clk_register_clkdev(clk, NULL, "timer");
|
|
|
|
/* Then this special MMC/SD clock */
|
|
clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
|
|
clk_register_clkdev(clk, NULL, "mmci");
|
|
}
|