112 lines
2.7 KiB
C
112 lines
2.7 KiB
C
#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "clk-icst.h"
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/*
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* Implementation of the ARM Integrator/AP and Integrator/CP clock tree.
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* Inspired by portions of:
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* plat-versatile/clock.c and plat-versatile/include/plat/clock.h
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*/
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#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
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#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
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/**
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* cp_auxvco_get() - get ICST VCO settings for the Integrator/CP
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* @vco: ICST VCO parameters to update with hardware status
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*/
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static struct icst_vco cp_auxvco_get(void)
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{
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u32 val;
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struct icst_vco vco;
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val = readl(CM_AUXOSC);
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vco.v = val & 0x1ff;
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vco.r = (val >> 9) & 0x7f;
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vco.s = (val >> 16) & 03;
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return vco;
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}
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/**
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* cp_auxvco_set() - commit changes to Integrator/CP ICST VCO
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* @vco: ICST VCO parameters to commit
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*/
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static void cp_auxvco_set(struct icst_vco vco)
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{
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u32 val;
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val = readl(CM_AUXOSC) & ~0x7ffff;
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val |= vco.v | (vco.r << 9) | (vco.s << 16);
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/* This magic unlocks the CM VCO so it can be controlled */
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writel(0xa05f, CM_LOCK);
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writel(val, CM_AUXOSC);
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/* This locks the CM again */
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writel(0, CM_LOCK);
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}
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static const struct icst_params cp_auxvco_params = {
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.ref = 24000000,
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.vco_max = ICST525_VCO_MAX_5V,
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.vco_min = ICST525_VCO_MIN,
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.vd_min = 8,
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.vd_max = 263,
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.rd_min = 3,
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.rd_max = 65,
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.s2div = icst525_s2div,
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.idx2s = icst525_idx2s,
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};
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static const struct clk_icst_desc __initdata cp_icst_desc = {
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.params = &cp_auxvco_params,
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.getvco = cp_auxvco_get,
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.setvco = cp_auxvco_set,
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};
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/*
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* integrator_clk_init() - set up the integrator clock tree
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* @is_cp: pass true if it's the Integrator/CP else AP is assumed
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*/
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void __init integrator_clk_init(bool is_cp)
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{
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struct clk *clk;
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/* APB clock dummy */
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clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
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clk_register_clkdev(clk, "apb_pclk", NULL);
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/* UART reference clock */
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clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT,
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14745600);
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clk_register_clkdev(clk, NULL, "uart0");
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clk_register_clkdev(clk, NULL, "uart1");
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if (is_cp)
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clk_register_clkdev(clk, NULL, "mmci");
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/* 24 MHz clock */
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clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
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24000000);
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clk_register_clkdev(clk, NULL, "kmi0");
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clk_register_clkdev(clk, NULL, "kmi1");
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if (!is_cp)
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clk_register_clkdev(clk, NULL, "ap_timer");
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if (!is_cp)
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return;
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/* 1 MHz clock */
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clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
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1000000);
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clk_register_clkdev(clk, NULL, "sp804");
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/* ICST VCO clock used on the Integrator/CP CLCD */
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clk = icst_clk_register(NULL, &cp_icst_desc);
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clk_register_clkdev(clk, NULL, "clcd");
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}
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