416 lines
11 KiB
C
416 lines
11 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_grctx.h"
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struct nouveau_channel *
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nv40_graph_channel(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t inst;
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int i;
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inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
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if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
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return NULL;
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inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
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for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
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struct nouveau_channel *chan = dev_priv->fifos[i];
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if (chan && chan->ramin_grctx &&
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chan->ramin_grctx->pinst == inst)
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return chan;
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}
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return NULL;
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}
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int
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nv40_graph_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_grctx ctx = {};
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int ret;
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ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
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NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
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if (ret)
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return ret;
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/* Initialise default context values */
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = chan->ramin_grctx;
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nv40_grctx_init(&ctx);
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nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
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return 0;
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}
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void
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nv40_graph_destroy_context(struct nouveau_channel *chan)
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{
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nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
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}
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static int
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nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
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{
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uint32_t old_cp, tv = 1000, tmp;
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int i;
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old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
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tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
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tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
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NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
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tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
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tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
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nouveau_wait_for_idle(dev);
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for (i = 0; i < tv; i++) {
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if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
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break;
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}
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
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if (i == tv) {
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uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
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NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
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NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
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ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
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ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
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NV_ERROR(dev, "0x40030C = 0x%08x\n",
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nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
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return -EBUSY;
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}
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return 0;
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}
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/* Restore the context for a specific channel into PGRAPH */
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int
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nv40_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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uint32_t inst;
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int ret;
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if (!chan->ramin_grctx)
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return -EINVAL;
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inst = chan->ramin_grctx->pinst >> 4;
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ret = nv40_graph_transfer_context(dev, inst, 0);
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if (ret)
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return ret;
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/* 0x40032C, no idea of it's exact function. Could simply be a
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* record of the currently active PGRAPH context. It's currently
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* unknown as to what bit 24 does. The nv ddx has it set, so we will
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* set it here too.
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*/
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
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(inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
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NV40_PGRAPH_CTXCTL_CUR_LOADED);
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/* 0x32E0 records the instance address of the active FIFO's PGRAPH
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* context. If at any time this doesn't match 0x40032C, you will
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* recieve PGRAPH_INTR_CONTEXT_SWITCH
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*/
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nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
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return 0;
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}
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int
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nv40_graph_unload_context(struct drm_device *dev)
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{
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uint32_t inst;
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int ret;
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inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
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if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
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return 0;
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inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
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ret = nv40_graph_transfer_context(dev, inst, 1);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
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return ret;
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}
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void
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nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t limit = max(1u, addr + size) - 1;
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if (pitch)
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addr |= 1;
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switch (dev_priv->chipset) {
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case 0x44:
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case 0x4a:
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case 0x4e:
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nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
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nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
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nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
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break;
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case 0x46:
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case 0x47:
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case 0x49:
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case 0x4b:
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nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
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nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
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nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
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nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
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nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
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nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
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break;
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default:
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nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
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nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
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nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
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nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
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nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
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nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
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break;
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}
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}
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/*
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* G70 0x47
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* G71 0x49
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* NV45 0x48
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* G72[M] 0x46
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* G73 0x4b
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* C51_G7X 0x4c
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* C51 0x4e
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*/
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int
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nv40_graph_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv =
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(struct drm_nouveau_private *)dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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struct nouveau_grctx ctx = {};
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uint32_t vramsz, *cp;
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int i, j;
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
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~NV_PMC_ENABLE_PGRAPH);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
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if (!cp)
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return -ENOMEM;
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = cp;
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ctx.ctxprog_max = 256;
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nv40_grctx_init(&ctx);
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dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
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kfree(cp);
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/* No context present currently */
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
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nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
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nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
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nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
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nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
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nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
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nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
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j = nv_rd32(dev, 0x1540) & 0xff;
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if (j) {
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for (i = 0; !(j & 1); j >>= 1, i++)
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;
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nv_wr32(dev, 0x405000, i);
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}
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if (dev_priv->chipset == 0x40) {
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nv_wr32(dev, 0x4009b0, 0x83280fff);
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nv_wr32(dev, 0x4009b4, 0x000000a0);
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} else {
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nv_wr32(dev, 0x400820, 0x83280eff);
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nv_wr32(dev, 0x400824, 0x000000a0);
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}
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x45:
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nv_wr32(dev, 0x4009b8, 0x0078e366);
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nv_wr32(dev, 0x4009bc, 0x0000014c);
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break;
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case 0x41:
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case 0x42: /* pciid also 0x00Cx */
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/* case 0x0120: XXX (pciid) */
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nv_wr32(dev, 0x400828, 0x007596ff);
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nv_wr32(dev, 0x40082c, 0x00000108);
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break;
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case 0x43:
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nv_wr32(dev, 0x400828, 0x0072cb77);
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nv_wr32(dev, 0x40082c, 0x00000108);
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break;
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case 0x44:
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case 0x46: /* G72 */
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case 0x4a:
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case 0x4c: /* G7x-based C51 */
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case 0x4e:
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nv_wr32(dev, 0x400860, 0);
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nv_wr32(dev, 0x400864, 0);
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break;
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
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nv_wr32(dev, 0x400828, 0x07830610);
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nv_wr32(dev, 0x40082c, 0x0000016A);
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break;
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default:
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break;
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}
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nv_wr32(dev, 0x400b38, 0x2ffff800);
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nv_wr32(dev, 0x400b3c, 0x00006000);
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/* Tiling related stuff. */
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switch (dev_priv->chipset) {
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case 0x44:
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case 0x4a:
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nv_wr32(dev, 0x400bc4, 0x1003d888);
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nv_wr32(dev, 0x400bbc, 0xb7a7b500);
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break;
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case 0x46:
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nv_wr32(dev, 0x400bc4, 0x0000e024);
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nv_wr32(dev, 0x400bbc, 0xb7a7b520);
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break;
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case 0x4c:
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case 0x4e:
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case 0x67:
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nv_wr32(dev, 0x400bc4, 0x1003d888);
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nv_wr32(dev, 0x400bbc, 0xb7a7b540);
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break;
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default:
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break;
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}
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/* Turn all the tiling regions off. */
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for (i = 0; i < pfb->num_tiles; i++)
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nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
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/* begin RAM config */
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vramsz = pci_resource_len(dev->pdev, 0) - 1;
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switch (dev_priv->chipset) {
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case 0x40:
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nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
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nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
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nv_wr32(dev, 0x400820, 0);
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nv_wr32(dev, 0x400824, 0);
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nv_wr32(dev, 0x400864, vramsz);
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nv_wr32(dev, 0x400868, vramsz);
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break;
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default:
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switch (dev_priv->chipset) {
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case 0x46:
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case 0x47:
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case 0x49:
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case 0x4b:
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nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
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break;
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default:
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nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
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break;
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}
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nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
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nv_wr32(dev, 0x400840, 0);
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nv_wr32(dev, 0x400844, 0);
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nv_wr32(dev, 0x4008A0, vramsz);
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nv_wr32(dev, 0x4008A4, vramsz);
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break;
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}
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return 0;
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}
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void nv40_graph_takedown(struct drm_device *dev)
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{
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}
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struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
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{ 0x0030, false, NULL }, /* null */
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{ 0x0039, false, NULL }, /* m2mf */
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{ 0x004a, false, NULL }, /* gdirect */
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{ 0x009f, false, NULL }, /* imageblit (nv12) */
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{ 0x008a, false, NULL }, /* ifc */
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{ 0x0089, false, NULL }, /* sifm */
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{ 0x3089, false, NULL }, /* sifm (nv40) */
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{ 0x0062, false, NULL }, /* surf2d */
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{ 0x3062, false, NULL }, /* surf2d (nv40) */
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{ 0x0043, false, NULL }, /* rop */
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{ 0x0012, false, NULL }, /* beta1 */
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{ 0x0072, false, NULL }, /* beta4 */
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{ 0x0019, false, NULL }, /* cliprect */
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{ 0x0044, false, NULL }, /* pattern */
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{ 0x309e, false, NULL }, /* swzsurf */
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{ 0x4097, false, NULL }, /* curie (nv40) */
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{ 0x4497, false, NULL }, /* curie (nv44) */
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{}
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};
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