98 lines
2.9 KiB
C
98 lines
2.9 KiB
C
#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#if __LINUX_ARM_ARCH__ >= 7 || \
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(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
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#define sev() __asm__ __volatile__ ("sev" : : : "memory")
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#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
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#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
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#endif
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#if __LINUX_ARM_ARCH__ >= 7
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#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
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#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
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#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
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#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
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#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#elif defined(CONFIG_CPU_FA526)
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#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
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#else
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#define isb(x) __asm__ __volatile__ ("" : : : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
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#endif
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#ifdef CONFIG_ARM_HEAVY_MB
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extern void (*soc_mb)(void);
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extern void arm_heavy_mb(void);
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#define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)
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#else
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#define __arm_heavy_mb(x...) dsb(x)
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#endif
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#ifdef CONFIG_ARCH_HAS_BARRIERS
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#include <mach/barriers.h>
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#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
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#define mb() __arm_heavy_mb()
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#define rmb() dsb()
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#define wmb() __arm_heavy_mb(st)
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#define dma_rmb() dmb(osh)
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#define dma_wmb() dmb(oshst)
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#else
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define dma_rmb() barrier()
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#define dma_wmb() barrier()
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#endif
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#ifndef CONFIG_SMP
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#else
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#define smp_mb() dmb(ish)
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#define smp_rmb() smp_mb()
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#define smp_wmb() dmb(ishst)
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#endif
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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___p1; \
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})
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_BARRIER_H */
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