572 lines
15 KiB
C
572 lines
15 KiB
C
/*
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* Toshiba TMIO NAND flash controller driver
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*
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* Slightly murky pre-git history of the driver:
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*
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* Copyright (c) Ian Molton 2004, 2005, 2008
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* Original work, independent of sharps code. Included hardware ECC support.
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* Hard ECC did not work for writes in the early revisions.
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* Copyright (c) Dirk Opfer 2005.
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* Modifications developed from sharps code but
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* NOT containing any, ported onto Ians base.
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* Copyright (c) Chris Humbert 2005
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* Copyright (c) Dmitry Baryshkov 2008
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* Minor fixes
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*
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* Parts copyright Sebastian Carlier
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*
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* This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/tmio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/slab.h>
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/*--------------------------------------------------------------------------*/
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/*
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* NAND Flash Host Controller Configuration Register
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*/
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#define CCR_COMMAND 0x04 /* w Command */
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#define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */
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#define CCR_INTP 0x3d /* b Interrupt Pin */
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#define CCR_INTE 0x48 /* b Interrupt Enable */
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#define CCR_EC 0x4a /* b Event Control */
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#define CCR_ICC 0x4c /* b Internal Clock Control */
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#define CCR_ECCC 0x5b /* b ECC Control */
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#define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */
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#define CCR_NFM 0x61 /* b NAND Flash Monitor */
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#define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */
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#define CCR_NFDC 0x63 /* b NAND Flash Detect Control */
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/*
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* NAND Flash Control Register
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*/
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#define FCR_DATA 0x00 /* bwl Data Register */
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#define FCR_MODE 0x04 /* b Mode Register */
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#define FCR_STATUS 0x05 /* b Status Register */
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#define FCR_ISR 0x06 /* b Interrupt Status Register */
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#define FCR_IMR 0x07 /* b Interrupt Mask Register */
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/* FCR_MODE Register Command List */
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#define FCR_MODE_DATA 0x94 /* Data Data_Mode */
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#define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */
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#define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */
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#define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
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#define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
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#define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
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#define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */
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#define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */
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#define FCR_MODE_LED_OFF 0x00 /* LED OFF */
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#define FCR_MODE_LED_ON 0x04 /* LED ON */
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#define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */
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#define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */
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#define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */
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#define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */
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#define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */
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#define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */
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#define FCR_MODE_WE 0x80
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#define FCR_MODE_ECC1 0x40
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#define FCR_MODE_ECC0 0x20
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#define FCR_MODE_CE 0x10
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#define FCR_MODE_PCNT1 0x08
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#define FCR_MODE_PCNT0 0x04
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#define FCR_MODE_ALE 0x02
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#define FCR_MODE_CLE 0x01
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#define FCR_STATUS_BUSY 0x80
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/*--------------------------------------------------------------------------*/
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struct tmio_nand {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct platform_device *dev;
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void __iomem *ccr;
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void __iomem *fcr;
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unsigned long fcr_base;
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unsigned int irq;
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/* for tmio_nand_read_byte */
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u8 read;
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unsigned read_good:1;
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};
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#define mtd_to_tmio(m) container_of(m, struct tmio_nand, mtd)
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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static const char *part_probes[] = { "cmdlinepart", NULL };
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#endif
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/*--------------------------------------------------------------------------*/
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static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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struct nand_chip *chip = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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u8 mode;
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if (ctrl & NAND_NCE) {
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mode = FCR_MODE_DATA;
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if (ctrl & NAND_CLE)
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mode |= FCR_MODE_CLE;
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else
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mode &= ~FCR_MODE_CLE;
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if (ctrl & NAND_ALE)
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mode |= FCR_MODE_ALE;
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else
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mode &= ~FCR_MODE_ALE;
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} else {
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mode = FCR_MODE_STANDBY;
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}
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tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
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tmio->read_good = 0;
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}
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if (cmd != NAND_CMD_NONE)
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tmio_iowrite8(cmd, chip->IO_ADDR_W);
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}
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static int tmio_nand_dev_ready(struct mtd_info *mtd)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
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}
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static irqreturn_t tmio_irq(int irq, void *__tmio)
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{
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struct tmio_nand *tmio = __tmio;
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struct nand_chip *nand_chip = &tmio->chip;
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/* disable RDYREQ interrupt */
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tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
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if (unlikely(!waitqueue_active(&nand_chip->controller->wq)))
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dev_warn(&tmio->dev->dev, "spurious interrupt\n");
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wake_up(&nand_chip->controller->wq);
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return IRQ_HANDLED;
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}
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/*
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*The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
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*This interrupt is normally disabled, but for long operations like
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*erase and write, we enable it to wake us up. The irq handler
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*disables the interrupt.
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*/
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static int
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tmio_nand_wait(struct mtd_info *mtd, struct nand_chip *nand_chip)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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long timeout;
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/* enable RDYREQ interrupt */
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tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
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tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
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timeout = wait_event_timeout(nand_chip->controller->wq,
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tmio_nand_dev_ready(mtd),
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msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20));
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if (unlikely(!tmio_nand_dev_ready(mtd))) {
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tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
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dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n",
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nand_chip->state == FL_ERASING ? "erase" : "program",
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nand_chip->state == FL_ERASING ? 400 : 20);
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} else if (unlikely(!timeout)) {
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tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
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dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
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}
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nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
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return nand_chip->read_byte(mtd);
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}
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/*
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*The TMIO controller combines two 8-bit data bytes into one 16-bit
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*word. This function separates them so nand_base.c works as expected,
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*especially its NAND_CMD_READID routines.
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*
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*To prevent stale data from being read, tmio_nand_hwcontrol() clears
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*tmio->read_good.
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*/
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static u_char tmio_nand_read_byte(struct mtd_info *mtd)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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unsigned int data;
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if (tmio->read_good--)
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return tmio->read;
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data = tmio_ioread16(tmio->fcr + FCR_DATA);
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tmio->read = data >> 8;
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return data;
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}
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/*
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*The TMIO controller converts an 8-bit NAND interface to a 16-bit
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*bus interface, so all data reads and writes must be 16-bit wide.
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*Thus, we implement 16-bit versions of the read, write, and verify
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*buffer functions.
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*/
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static void
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tmio_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
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}
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static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
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}
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static int
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tmio_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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u16 *p = (u16 *) buf;
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for (len >>= 1; len; len--)
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if (*(p++) != tmio_ioread16(tmio->fcr + FCR_DATA))
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return -EFAULT;
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return 0;
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}
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static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
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tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
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tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
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}
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static int tmio_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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struct tmio_nand *tmio = mtd_to_tmio(mtd);
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unsigned int ecc;
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tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
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ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
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ecc_code[1] = ecc; /* 000-255 LP7-0 */
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ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */
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ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
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ecc_code[2] = ecc; /* 000-255 CP5-0,11b */
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ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */
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ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
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ecc_code[3] = ecc; /* 256-511 LP15-8 */
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ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */
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tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
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return 0;
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}
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static int tmio_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
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unsigned char *read_ecc, unsigned char *calc_ecc)
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{
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int r0, r1;
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/* assume ecc.size = 512 and ecc.bytes = 6 */
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r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
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if (r0 < 0)
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return r0;
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r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256);
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if (r1 < 0)
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return r1;
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return r0 + r1;
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}
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static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
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{
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const struct mfd_cell *cell = mfd_get_cell(dev);
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int ret;
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if (cell->enable) {
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ret = cell->enable(dev);
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if (ret)
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return ret;
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}
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/* (4Ch) CLKRUN Enable 1st spcrunc */
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tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
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/* (10h)BaseAddress 0x1000 spba.spba2 */
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tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
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tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
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/* (04h)Command Register I/O spcmd */
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tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
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/* (62h) Power Supply Control ssmpwc */
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/* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
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tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
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/* (63h) Detect Control ssmdtc */
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tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
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/* Interrupt status register clear sintst */
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tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
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/* After power supply, Media are reset smode */
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tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
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tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
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tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
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/* Standby Mode smode */
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tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
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mdelay(5);
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return 0;
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}
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static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
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{
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const struct mfd_cell *cell = mfd_get_cell(dev);
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tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
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if (cell->disable)
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cell->disable(dev);
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}
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static int tmio_probe(struct platform_device *dev)
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{
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struct tmio_nand_data *data = mfd_get_data(dev);
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struct resource *fcr = platform_get_resource(dev,
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IORESOURCE_MEM, 0);
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struct resource *ccr = platform_get_resource(dev,
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IORESOURCE_MEM, 1);
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int irq = platform_get_irq(dev, 0);
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struct tmio_nand *tmio;
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struct mtd_info *mtd;
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struct nand_chip *nand_chip;
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#ifdef CONFIG_MTD_PARTITIONS
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struct mtd_partition *parts;
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int nbparts = 0;
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#endif
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int retval;
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if (data == NULL)
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dev_warn(&dev->dev, "NULL platform data!\n");
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tmio = kzalloc(sizeof *tmio, GFP_KERNEL);
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if (!tmio) {
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retval = -ENOMEM;
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goto err_kzalloc;
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}
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tmio->dev = dev;
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platform_set_drvdata(dev, tmio);
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mtd = &tmio->mtd;
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nand_chip = &tmio->chip;
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mtd->priv = nand_chip;
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mtd->name = "tmio-nand";
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tmio->ccr = ioremap(ccr->start, resource_size(ccr));
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if (!tmio->ccr) {
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retval = -EIO;
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goto err_iomap_ccr;
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}
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tmio->fcr_base = fcr->start & 0xfffff;
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tmio->fcr = ioremap(fcr->start, resource_size(fcr));
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if (!tmio->fcr) {
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retval = -EIO;
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goto err_iomap_fcr;
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}
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retval = tmio_hw_init(dev, tmio);
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if (retval)
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goto err_hwinit;
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/* Set address of NAND IO lines */
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nand_chip->IO_ADDR_R = tmio->fcr;
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nand_chip->IO_ADDR_W = tmio->fcr;
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/* Set address of hardware control function */
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nand_chip->cmd_ctrl = tmio_nand_hwcontrol;
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nand_chip->dev_ready = tmio_nand_dev_ready;
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nand_chip->read_byte = tmio_nand_read_byte;
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nand_chip->write_buf = tmio_nand_write_buf;
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nand_chip->read_buf = tmio_nand_read_buf;
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nand_chip->verify_buf = tmio_nand_verify_buf;
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/* set eccmode using hardware ECC */
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nand_chip->ecc.mode = NAND_ECC_HW;
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nand_chip->ecc.size = 512;
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nand_chip->ecc.bytes = 6;
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nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
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nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
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nand_chip->ecc.correct = tmio_nand_correct_data;
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if (data)
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nand_chip->badblock_pattern = data->badblock_pattern;
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/* 15 us command delay time */
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nand_chip->chip_delay = 15;
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retval = request_irq(irq, &tmio_irq,
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IRQF_DISABLED, dev_name(&dev->dev), tmio);
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if (retval) {
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dev_err(&dev->dev, "request_irq error %d\n", retval);
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goto err_irq;
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}
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tmio->irq = irq;
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nand_chip->waitfunc = tmio_nand_wait;
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/* Scan to find existence of the device */
|
|
if (nand_scan(mtd, 1)) {
|
|
retval = -ENODEV;
|
|
goto err_scan;
|
|
}
|
|
/* Register the partitions */
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
#ifdef CONFIG_MTD_CMDLINE_PARTS
|
|
nbparts = parse_mtd_partitions(mtd, part_probes, &parts, 0);
|
|
#endif
|
|
if (nbparts <= 0 && data) {
|
|
parts = data->partition;
|
|
nbparts = data->num_partitions;
|
|
}
|
|
|
|
if (nbparts)
|
|
retval = add_mtd_partitions(mtd, parts, nbparts);
|
|
else
|
|
#endif
|
|
retval = add_mtd_device(mtd);
|
|
|
|
if (!retval)
|
|
return retval;
|
|
|
|
nand_release(mtd);
|
|
|
|
err_scan:
|
|
if (tmio->irq)
|
|
free_irq(tmio->irq, tmio);
|
|
err_irq:
|
|
tmio_hw_stop(dev, tmio);
|
|
err_hwinit:
|
|
iounmap(tmio->fcr);
|
|
err_iomap_fcr:
|
|
iounmap(tmio->ccr);
|
|
err_iomap_ccr:
|
|
kfree(tmio);
|
|
err_kzalloc:
|
|
return retval;
|
|
}
|
|
|
|
static int tmio_remove(struct platform_device *dev)
|
|
{
|
|
struct tmio_nand *tmio = platform_get_drvdata(dev);
|
|
|
|
nand_release(&tmio->mtd);
|
|
if (tmio->irq)
|
|
free_irq(tmio->irq, tmio);
|
|
tmio_hw_stop(dev, tmio);
|
|
iounmap(tmio->fcr);
|
|
iounmap(tmio->ccr);
|
|
kfree(tmio);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int tmio_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
const struct mfd_cell *cell = mfd_get_cell(dev);
|
|
|
|
if (cell->suspend)
|
|
cell->suspend(dev);
|
|
|
|
tmio_hw_stop(dev, platform_get_drvdata(dev));
|
|
return 0;
|
|
}
|
|
|
|
static int tmio_resume(struct platform_device *dev)
|
|
{
|
|
const struct mfd_cell *cell = mfd_get_cell(dev);
|
|
|
|
/* FIXME - is this required or merely another attack of the broken
|
|
* SHARP platform? Looks suspicious.
|
|
*/
|
|
tmio_hw_init(dev, platform_get_drvdata(dev));
|
|
|
|
if (cell->resume)
|
|
cell->resume(dev);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define tmio_suspend NULL
|
|
#define tmio_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver tmio_driver = {
|
|
.driver.name = "tmio-nand",
|
|
.driver.owner = THIS_MODULE,
|
|
.probe = tmio_probe,
|
|
.remove = tmio_remove,
|
|
.suspend = tmio_suspend,
|
|
.resume = tmio_resume,
|
|
};
|
|
|
|
static int __init tmio_init(void)
|
|
{
|
|
return platform_driver_register(&tmio_driver);
|
|
}
|
|
|
|
static void __exit tmio_exit(void)
|
|
{
|
|
platform_driver_unregister(&tmio_driver);
|
|
}
|
|
|
|
module_init(tmio_init);
|
|
module_exit(tmio_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
|
|
MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
|
|
MODULE_ALIAS("platform:tmio-nand");
|