448 lines
14 KiB
C
448 lines
14 KiB
C
/*
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* Host interface registers
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*/
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#define OXU_DEVICEID 0x00
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#define OXU_REV_MASK 0xffff0000
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#define OXU_REV_SHIFT 16
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#define OXU_REV_2100 0x2100
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#define OXU_BO_SHIFT 8
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#define OXU_BO_MASK (0x3 << OXU_BO_SHIFT)
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#define OXU_MAJ_REV_SHIFT 4
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#define OXU_MAJ_REV_MASK (0xf << OXU_MAJ_REV_SHIFT)
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#define OXU_MIN_REV_SHIFT 0
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#define OXU_MIN_REV_MASK (0xf << OXU_MIN_REV_SHIFT)
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#define OXU_HOSTIFCONFIG 0x04
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#define OXU_SOFTRESET 0x08
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#define OXU_SRESET (1 << 0)
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#define OXU_PIOBURSTREADCTRL 0x0C
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#define OXU_CHIPIRQSTATUS 0x10
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#define OXU_CHIPIRQEN_SET 0x14
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#define OXU_CHIPIRQEN_CLR 0x18
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#define OXU_USBSPHLPWUI 0x00000080
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#define OXU_USBOTGLPWUI 0x00000040
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#define OXU_USBSPHI 0x00000002
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#define OXU_USBOTGI 0x00000001
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#define OXU_CLKCTRL_SET 0x1C
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#define OXU_SYSCLKEN 0x00000008
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#define OXU_USBSPHCLKEN 0x00000002
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#define OXU_USBOTGCLKEN 0x00000001
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#define OXU_ASO 0x68
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#define OXU_SPHPOEN 0x00000100
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#define OXU_OVRCCURPUPDEN 0x00000800
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#define OXU_ASO_OP (1 << 10)
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#define OXU_COMPARATOR 0x000004000
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#define OXU_USBMODE 0x1A8
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#define OXU_VBPS 0x00000020
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#define OXU_ES_LITTLE 0x00000000
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#define OXU_CM_HOST_ONLY 0x00000003
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/*
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* Proper EHCI structs & defines
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*/
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/* Magic numbers that can affect system performance */
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#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
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#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
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#define EHCI_TUNE_RL_TT 0
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#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
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#define EHCI_TUNE_MULT_TT 1
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#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
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struct oxu_hcd;
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/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
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/* Section 2.2 Host Controller Capability Registers */
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struct ehci_caps {
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/* these fields are specified as 8 and 16 bit registers,
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* but some hosts can't perform 8 or 16 bit PCI accesses.
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*/
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u32 hc_capbase;
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#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
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#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
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u32 hcs_params; /* HCSPARAMS - offset 0x4 */
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#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
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#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
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#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
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#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
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#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
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#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
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#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
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u32 hcc_params; /* HCCPARAMS - offset 0x8 */
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#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
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#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
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#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
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#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
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#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
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#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
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u8 portroute[8]; /* nibbles for routing - offset 0xC */
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} __attribute__ ((packed));
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/* Section 2.3 Host Controller Operational Registers */
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struct ehci_regs {
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/* USBCMD: offset 0x00 */
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u32 command;
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/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
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#define CMD_PARK (1<<11) /* enable "park" on async qh */
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#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
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#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
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#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
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#define CMD_ASE (1<<5) /* async schedule enable */
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#define CMD_PSE (1<<4) /* periodic schedule enable */
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/* 3:2 is periodic frame list size */
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#define CMD_RESET (1<<1) /* reset HC not bus */
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#define CMD_RUN (1<<0) /* start/stop HC */
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/* USBSTS: offset 0x04 */
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u32 status;
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#define STS_ASS (1<<15) /* Async Schedule Status */
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#define STS_PSS (1<<14) /* Periodic Schedule Status */
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#define STS_RECL (1<<13) /* Reclamation */
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#define STS_HALT (1<<12) /* Not running (any reason) */
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/* some bits reserved */
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/* these STS_* flags are also intr_enable bits (USBINTR) */
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#define STS_IAA (1<<5) /* Interrupted on async advance */
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#define STS_FATAL (1<<4) /* such as some PCI access errors */
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#define STS_FLR (1<<3) /* frame list rolled over */
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#define STS_PCD (1<<2) /* port change detect */
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#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
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#define STS_INT (1<<0) /* "normal" completion (short, ...) */
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#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
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/* USBINTR: offset 0x08 */
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u32 intr_enable;
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/* FRINDEX: offset 0x0C */
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u32 frame_index; /* current microframe number */
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/* CTRLDSSEGMENT: offset 0x10 */
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u32 segment; /* address bits 63:32 if needed */
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/* PERIODICLISTBASE: offset 0x14 */
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u32 frame_list; /* points to periodic list */
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/* ASYNCLISTADDR: offset 0x18 */
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u32 async_next; /* address of next async queue head */
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u32 reserved[9];
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/* CONFIGFLAG: offset 0x40 */
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u32 configured_flag;
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#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
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/* PORTSC: offset 0x44 */
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u32 port_status[0]; /* up to N_PORTS */
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/* 31:23 reserved */
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#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
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#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
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#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
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/* 19:16 for port testing */
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#define PORT_LED_OFF (0<<14)
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#define PORT_LED_AMBER (1<<14)
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#define PORT_LED_GREEN (2<<14)
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#define PORT_LED_MASK (3<<14)
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#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
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#define PORT_POWER (1<<12) /* true: has power (see PPC) */
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#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
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/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
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/* 9 reserved */
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#define PORT_RESET (1<<8) /* reset port */
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#define PORT_SUSPEND (1<<7) /* suspend port */
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#define PORT_RESUME (1<<6) /* resume it */
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#define PORT_OCC (1<<5) /* over current change */
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#define PORT_OC (1<<4) /* over current active */
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#define PORT_PEC (1<<3) /* port enable change */
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#define PORT_PE (1<<2) /* port enable */
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#define PORT_CSC (1<<1) /* connect status change */
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#define PORT_CONNECT (1<<0) /* device connected */
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#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
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} __attribute__ ((packed));
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/* Appendix C, Debug port ... intended for use with special "debug devices"
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* that can help if there's no serial console. (nonstandard enumeration.)
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*/
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struct ehci_dbg_port {
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u32 control;
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#define DBGP_OWNER (1<<30)
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#define DBGP_ENABLED (1<<28)
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#define DBGP_DONE (1<<16)
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#define DBGP_INUSE (1<<10)
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#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
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# define DBGP_ERR_BAD 1
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# define DBGP_ERR_SIGNAL 2
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#define DBGP_ERROR (1<<6)
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#define DBGP_GO (1<<5)
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#define DBGP_OUT (1<<4)
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#define DBGP_LEN(x) (((x)>>0)&0x0f)
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u32 pids;
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#define DBGP_PID_GET(x) (((x)>>16)&0xff)
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#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
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u32 data03;
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u32 data47;
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u32 address;
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#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
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} __attribute__ ((packed));
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#define QTD_NEXT(dma) cpu_to_le32((u32)dma)
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/*
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* EHCI Specification 0.95 Section 3.5
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* QTD: describe data transfer components (buffer, direction, ...)
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* See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
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*
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* These are associated only with "QH" (Queue Head) structures,
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* used with control, bulk, and interrupt transfers.
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*/
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struct ehci_qtd {
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/* first part defined by EHCI spec */
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__le32 hw_next; /* see EHCI 3.5.1 */
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__le32 hw_alt_next; /* see EHCI 3.5.2 */
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__le32 hw_token; /* see EHCI 3.5.3 */
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#define QTD_TOGGLE (1 << 31) /* data toggle */
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#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
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#define QTD_IOC (1 << 15) /* interrupt on complete */
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#define QTD_CERR(tok) (((tok)>>10) & 0x3)
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#define QTD_PID(tok) (((tok)>>8) & 0x3)
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#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
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#define QTD_STS_HALT (1 << 6) /* halted on error */
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#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
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#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
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#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
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#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
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#define QTD_STS_STS (1 << 1) /* split transaction state */
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#define QTD_STS_PING (1 << 0) /* issue PING? */
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__le32 hw_buf[5]; /* see EHCI 3.5.4 */
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__le32 hw_buf_hi[5]; /* Appendix B */
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/* the rest is HCD-private */
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dma_addr_t qtd_dma; /* qtd address */
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struct list_head qtd_list; /* sw qtd list */
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struct urb *urb; /* qtd's urb */
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size_t length; /* length of buffer */
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u32 qtd_buffer_len;
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void *buffer;
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dma_addr_t buffer_dma;
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void *transfer_buffer;
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void *transfer_dma;
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} __attribute__ ((aligned(32)));
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/* mask NakCnt+T in qh->hw_alt_next */
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#define QTD_MASK cpu_to_le32 (~0x1f)
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#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
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/* Type tag from {qh, itd, sitd, fstn}->hw_next */
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#define Q_NEXT_TYPE(dma) ((dma) & cpu_to_le32 (3 << 1))
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/* values for that type tag */
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#define Q_TYPE_QH cpu_to_le32 (1 << 1)
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/* next async queue entry, or pointer to interrupt/periodic QH */
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#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
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/* for periodic/async schedules and qtd lists, mark end of list */
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#define EHCI_LIST_END cpu_to_le32(1) /* "null pointer" to hw */
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/*
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* Entries in periodic shadow table are pointers to one of four kinds
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* of data structure. That's dictated by the hardware; a type tag is
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* encoded in the low bits of the hardware's periodic schedule. Use
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* Q_NEXT_TYPE to get the tag.
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*
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* For entries in the async schedule, the type tag always says "qh".
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*/
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union ehci_shadow {
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struct ehci_qh *qh; /* Q_TYPE_QH */
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__le32 *hw_next; /* (all types) */
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void *ptr;
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};
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/*
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* EHCI Specification 0.95 Section 3.6
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* QH: describes control/bulk/interrupt endpoints
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* See Fig 3-7 "Queue Head Structure Layout".
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*
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* These appear in both the async and (for interrupt) periodic schedules.
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*/
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struct ehci_qh {
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/* first part defined by EHCI spec */
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__le32 hw_next; /* see EHCI 3.6.1 */
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__le32 hw_info1; /* see EHCI 3.6.2 */
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#define QH_HEAD 0x00008000
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__le32 hw_info2; /* see EHCI 3.6.2 */
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#define QH_SMASK 0x000000ff
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#define QH_CMASK 0x0000ff00
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#define QH_HUBADDR 0x007f0000
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#define QH_HUBPORT 0x3f800000
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#define QH_MULT 0xc0000000
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__le32 hw_current; /* qtd list - see EHCI 3.6.4 */
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/* qtd overlay (hardware parts of a struct ehci_qtd) */
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__le32 hw_qtd_next;
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__le32 hw_alt_next;
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__le32 hw_token;
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__le32 hw_buf[5];
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__le32 hw_buf_hi[5];
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/* the rest is HCD-private */
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dma_addr_t qh_dma; /* address of qh */
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union ehci_shadow qh_next; /* ptr to qh; or periodic */
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struct list_head qtd_list; /* sw qtd list */
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struct ehci_qtd *dummy;
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struct ehci_qh *reclaim; /* next to reclaim */
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struct oxu_hcd *oxu;
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struct kref kref;
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unsigned stamp;
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u8 qh_state;
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#define QH_STATE_LINKED 1 /* HC sees this */
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#define QH_STATE_UNLINK 2 /* HC may still see this */
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#define QH_STATE_IDLE 3 /* HC doesn't see this */
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#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
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#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
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/* periodic schedule info */
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u8 usecs; /* intr bandwidth */
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u8 gap_uf; /* uframes split/csplit gap */
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u8 c_usecs; /* ... split completion bw */
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u16 tt_usecs; /* tt downstream bandwidth */
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unsigned short period; /* polling interval */
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unsigned short start; /* where polling starts */
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#define NO_FRAME ((unsigned short)~0) /* pick new start */
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struct usb_device *dev; /* access to TT */
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} __attribute__ ((aligned(32)));
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/*
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* Proper OXU210HP structs
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*/
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#define OXU_OTG_CORE_OFFSET 0x00400
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#define OXU_OTG_CAP_OFFSET (OXU_OTG_CORE_OFFSET + 0x100)
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#define OXU_SPH_CORE_OFFSET 0x00800
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#define OXU_SPH_CAP_OFFSET (OXU_SPH_CORE_OFFSET + 0x100)
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#define OXU_OTG_MEM 0xE000
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#define OXU_SPH_MEM 0x16000
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/* Only how many elements & element structure are specifies here. */
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/* 2 host controllers are enabled - total size <= 28 kbytes */
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#define DEFAULT_I_TDPS 1024
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#define QHEAD_NUM 16
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#define QTD_NUM 32
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#define SITD_NUM 8
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#define MURB_NUM 8
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#define BUFFER_NUM 8
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#define BUFFER_SIZE 512
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struct oxu_info {
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struct usb_hcd *hcd[2];
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};
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struct oxu_buf {
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u8 buffer[BUFFER_SIZE];
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} __attribute__ ((aligned(BUFFER_SIZE)));
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struct oxu_onchip_mem {
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struct oxu_buf db_pool[BUFFER_NUM];
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u32 frame_list[DEFAULT_I_TDPS];
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struct ehci_qh qh_pool[QHEAD_NUM];
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struct ehci_qtd qtd_pool[QTD_NUM];
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} __attribute__ ((aligned(4 << 10)));
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#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
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struct oxu_murb {
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struct urb urb;
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struct urb *main;
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u8 last;
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};
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struct oxu_hcd { /* one per controller */
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unsigned int is_otg:1;
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u8 qh_used[QHEAD_NUM];
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u8 qtd_used[QTD_NUM];
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u8 db_used[BUFFER_NUM];
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u8 murb_used[MURB_NUM];
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struct oxu_onchip_mem __iomem *mem;
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spinlock_t mem_lock;
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struct timer_list urb_timer;
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struct ehci_caps __iomem *caps;
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struct ehci_regs __iomem *regs;
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__u32 hcs_params; /* cached register copy */
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spinlock_t lock;
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/* async schedule support */
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struct ehci_qh *async;
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struct ehci_qh *reclaim;
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unsigned reclaim_ready:1;
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unsigned scanning:1;
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/* periodic schedule support */
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unsigned periodic_size;
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__le32 *periodic; /* hw periodic table */
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dma_addr_t periodic_dma;
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unsigned i_thresh; /* uframes HC might cache */
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union ehci_shadow *pshadow; /* mirror hw periodic table */
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int next_uframe; /* scan periodic, start here */
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unsigned periodic_sched; /* periodic activity count */
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/* per root hub port */
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unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
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/* bit vectors (one bit per port) */
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unsigned long bus_suspended; /* which ports were
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* already suspended at the
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* start of a bus suspend
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*/
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unsigned long companion_ports;/* which ports are dedicated
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* to the companion controller
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*/
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struct timer_list watchdog;
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unsigned long actions;
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unsigned stamp;
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unsigned long next_statechange;
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u32 command;
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/* SILICON QUIRKS */
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struct list_head urb_list; /* this is the head to urb
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* queue that didn't get enough
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* resources
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*/
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struct oxu_murb *murb_pool; /* murb per split big urb */
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unsigned urb_len;
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u8 sbrn; /* packed release number */
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};
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#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
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#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
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#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
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#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
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enum ehci_timer_action {
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TIMER_IO_WATCHDOG,
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TIMER_IAA_WATCHDOG,
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TIMER_ASYNC_SHRINK,
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TIMER_ASYNC_OFF,
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};
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#include <linux/oxu210hp.h>
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