485 lines
7.4 KiB
ArmAsm
485 lines
7.4 KiB
ArmAsm
/*
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* arch/xtensa/mm/misc.S
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*
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* Miscellaneous assembly functions.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2007 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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*/
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#include <linux/linkage.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheasm.h>
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#include <asm/tlbflush.h>
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/*
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* clear_page and clear_user_page are the same for non-cache-aliased configs.
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*
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* clear_page (unsigned long page)
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* a2
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*/
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ENTRY(clear_page)
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entry a1, 16
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movi a3, 0
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__loopi a2, a7, PAGE_SIZE, 32
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s32i a3, a2, 0
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s32i a3, a2, 4
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s32i a3, a2, 8
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s32i a3, a2, 12
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s32i a3, a2, 16
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s32i a3, a2, 20
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s32i a3, a2, 24
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s32i a3, a2, 28
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__endla a2, a7, 32
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retw
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ENDPROC(clear_page)
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/*
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* copy_page and copy_user_page are the same for non-cache-aliased configs.
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*
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* copy_page (void *to, void *from)
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* a2 a3
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*/
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ENTRY(copy_page)
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entry a1, 16
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__loopi a2, a4, PAGE_SIZE, 32
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l32i a8, a3, 0
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l32i a9, a3, 4
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s32i a8, a2, 0
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s32i a9, a2, 4
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l32i a8, a3, 8
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l32i a9, a3, 12
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s32i a8, a2, 8
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s32i a9, a2, 12
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l32i a8, a3, 16
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l32i a9, a3, 20
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s32i a8, a2, 16
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s32i a9, a2, 20
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l32i a8, a3, 24
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l32i a9, a3, 28
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s32i a8, a2, 24
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s32i a9, a2, 28
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addi a2, a2, 32
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addi a3, a3, 32
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__endl a2, a4
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retw
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ENDPROC(copy_page)
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#ifdef CONFIG_MMU
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/*
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* If we have to deal with cache aliasing, we use temporary memory mappings
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* to ensure that the source and destination pages have the same color as
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* the virtual address. We use way 0 and 1 for temporary mappings in such cases.
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*
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* The temporary DTLB entries shouldn't be flushed by interrupts, but are
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* flushed by preemptive task switches. Special code in the
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* fast_second_level_miss handler re-established the temporary mapping.
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* It requires that the PPNs for the destination and source addresses are
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* in a6, and a7, respectively.
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*/
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/* TLB miss exceptions are treated special in the following region */
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ENTRY(__tlbtemp_mapping_start)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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/*
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* clear_page_alias(void *addr, unsigned long paddr)
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* a2 a3
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*/
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ENTRY(clear_page_alias)
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entry a1, 32
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/* Skip setting up a temporary DTLB if not aliased low page. */
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movi a5, PAGE_OFFSET
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movi a6, 0
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beqz a3, 1f
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/* Setup a temporary DTLB for the addr. */
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addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
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mov a4, a2
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wdtlb a6, a2
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dsync
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1: movi a3, 0
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__loopi a2, a7, PAGE_SIZE, 32
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s32i a3, a2, 0
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s32i a3, a2, 4
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s32i a3, a2, 8
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s32i a3, a2, 12
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s32i a3, a2, 16
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s32i a3, a2, 20
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s32i a3, a2, 24
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s32i a3, a2, 28
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__endla a2, a7, 32
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bnez a6, 1f
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retw
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/* We need to invalidate the temporary idtlb entry, if any. */
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1: idtlb a4
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dsync
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retw
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ENDPROC(clear_page_alias)
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/*
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* copy_page_alias(void *to, void *from,
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* a2 a3
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* unsigned long to_paddr, unsigned long from_paddr)
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* a4 a5
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*/
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ENTRY(copy_page_alias)
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entry a1, 32
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/* Skip setting up a temporary DTLB for destination if not aliased. */
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movi a6, 0
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movi a7, 0
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beqz a4, 1f
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/* Setup a temporary DTLB for destination. */
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addi a6, a4, (PAGE_KERNEL | _PAGE_HW_WRITE)
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wdtlb a6, a2
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dsync
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/* Skip setting up a temporary DTLB for source if not aliased. */
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1: beqz a5, 1f
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/* Setup a temporary DTLB for source. */
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addi a7, a5, PAGE_KERNEL
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addi a8, a3, 1 # way1
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wdtlb a7, a8
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dsync
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1: __loopi a2, a4, PAGE_SIZE, 32
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l32i a8, a3, 0
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l32i a9, a3, 4
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s32i a8, a2, 0
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s32i a9, a2, 4
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l32i a8, a3, 8
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l32i a9, a3, 12
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s32i a8, a2, 8
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s32i a9, a2, 12
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l32i a8, a3, 16
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l32i a9, a3, 20
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s32i a8, a2, 16
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s32i a9, a2, 20
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l32i a8, a3, 24
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l32i a9, a3, 28
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s32i a8, a2, 24
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s32i a9, a2, 28
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addi a2, a2, 32
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addi a3, a3, 32
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__endl a2, a4
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/* We need to invalidate any temporary mapping! */
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bnez a6, 1f
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bnez a7, 2f
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retw
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1: addi a2, a2, -PAGE_SIZE
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idtlb a2
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dsync
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bnez a7, 2f
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retw
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2: addi a3, a3, -PAGE_SIZE+1
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idtlb a3
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dsync
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retw
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ENDPROC(copy_page_alias)
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#endif
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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/*
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* void __flush_invalidate_dcache_page_alias (addr, phys)
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* a2 a3
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*/
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ENTRY(__flush_invalidate_dcache_page_alias)
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entry sp, 16
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movi a7, 0 # required for exception handler
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addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
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mov a4, a2
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wdtlb a6, a2
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dsync
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___flush_invalidate_dcache_page a2 a3
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idtlb a4
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dsync
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retw
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ENDPROC(__flush_invalidate_dcache_page_alias)
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/*
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* void __invalidate_dcache_page_alias (addr, phys)
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* a2 a3
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*/
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ENTRY(__invalidate_dcache_page_alias)
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entry sp, 16
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movi a7, 0 # required for exception handler
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addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
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mov a4, a2
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wdtlb a6, a2
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dsync
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___invalidate_dcache_page a2 a3
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idtlb a4
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dsync
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retw
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ENDPROC(__invalidate_dcache_page_alias)
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#endif
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ENTRY(__tlbtemp_mapping_itlb)
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#if (ICACHE_WAY_SIZE > PAGE_SIZE)
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ENTRY(__invalidate_icache_page_alias)
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entry sp, 16
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addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
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mov a4, a2
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witlb a6, a2
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isync
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___invalidate_icache_page a2 a3
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iitlb a4
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isync
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retw
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ENDPROC(__invalidate_icache_page_alias)
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#endif
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/* End of special treatment in tlb miss exception */
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ENTRY(__tlbtemp_mapping_end)
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#endif /* CONFIG_MMU
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/*
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* void __invalidate_icache_page(ulong start)
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*/
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ENTRY(__invalidate_icache_page)
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entry sp, 16
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___invalidate_icache_page a2 a3
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isync
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retw
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ENDPROC(__invalidate_icache_page)
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/*
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* void __invalidate_dcache_page(ulong start)
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*/
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ENTRY(__invalidate_dcache_page)
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entry sp, 16
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___invalidate_dcache_page a2 a3
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dsync
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retw
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ENDPROC(__invalidate_dcache_page)
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/*
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* void __flush_invalidate_dcache_page(ulong start)
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*/
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ENTRY(__flush_invalidate_dcache_page)
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entry sp, 16
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___flush_invalidate_dcache_page a2 a3
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dsync
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retw
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ENDPROC(__flush_invalidate_dcache_page)
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/*
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* void __flush_dcache_page(ulong start)
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*/
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ENTRY(__flush_dcache_page)
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entry sp, 16
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___flush_dcache_page a2 a3
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dsync
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retw
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ENDPROC(__flush_dcache_page)
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/*
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* void __invalidate_icache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_icache_range)
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entry sp, 16
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___invalidate_icache_range a2 a3 a4
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isync
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retw
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ENDPROC(__invalidate_icache_range)
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/*
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* void __flush_invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_invalidate_dcache_range)
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entry sp, 16
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___flush_invalidate_dcache_range a2 a3 a4
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dsync
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retw
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ENDPROC(__flush_invalidate_dcache_range)
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/*
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* void _flush_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_dcache_range)
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entry sp, 16
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___flush_dcache_range a2 a3 a4
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dsync
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retw
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ENDPROC(__flush_dcache_range)
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/*
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* void _invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_dcache_range)
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entry sp, 16
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___invalidate_dcache_range a2 a3 a4
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retw
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ENDPROC(__invalidate_dcache_range)
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/*
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* void _invalidate_icache_all(void)
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*/
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ENTRY(__invalidate_icache_all)
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entry sp, 16
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___invalidate_icache_all a2 a3
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isync
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retw
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ENDPROC(__invalidate_icache_all)
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/*
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* void _flush_invalidate_dcache_all(void)
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*/
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ENTRY(__flush_invalidate_dcache_all)
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entry sp, 16
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___flush_invalidate_dcache_all a2 a3
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dsync
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retw
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ENDPROC(__flush_invalidate_dcache_all)
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/*
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* void _invalidate_dcache_all(void)
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*/
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ENTRY(__invalidate_dcache_all)
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entry sp, 16
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___invalidate_dcache_all a2 a3
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dsync
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retw
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ENDPROC(__invalidate_dcache_all)
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